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object SystemVerilogLexerSyntaxHighlighter

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  1. final def !=(arg0: Any): Boolean
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  2. final def ##: Int
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  4. val SYSTEMVERILOG_BLOCK_COMMENT: TextAttributesKey
  5. val SYSTEMVERILOG_COMMA: TextAttributesKey
  6. val SYSTEMVERILOG_DIRECTIVE: TextAttributesKey
  7. val SYSTEMVERILOG_DOLLAR_IDENTIFIER: TextAttributesKey
  8. val SYSTEMVERILOG_IDENTIFIER: TextAttributesKey
  9. val SYSTEMVERILOG_KEYWORD: TextAttributesKey
  10. val SYSTEMVERILOG_LINE_COMMENT: TextAttributesKey
  11. val SYSTEMVERILOG_MODULE_IDENTIFIER: TextAttributesKey
  12. val SYSTEMVERILOG_MODULE_INSTANTIATION: TextAttributesKey
  13. val SYSTEMVERILOG_NUMBER: TextAttributesKey
  14. val SYSTEMVERILOG_PORT_INOUT: TextAttributesKey
  15. val SYSTEMVERILOG_PORT_INPUT: TextAttributesKey
  16. val SYSTEMVERILOG_PORT_OUTPUT: TextAttributesKey
  17. val SYSTEMVERILOG_PORT_OUTPUT_REG: TextAttributesKey
  18. val SYSTEMVERILOG_SEMICOLON: TextAttributesKey
  19. val SYSTEMVERILOG_SIGNAL_NET: TextAttributesKey
  20. val SYSTEMVERILOG_SIGNAL_PARAMETER: TextAttributesKey
  21. val SYSTEMVERILOG_SIGNAL_REG: TextAttributesKey
  22. val SYSTEMVERILOG_STRING: TextAttributesKey
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