SystemVerilogParserVisitor

trait SystemVerilogParserVisitor[T] extends ParseTreeVisitor[T]

This interface defines a complete generic visitor for a parse tree produced by SystemVerilogParser.

Linear Supertypes

ParseTreeVisitor[T], AnyRef, Any

Known Subclasses

SystemVerilogParserBaseVisitor

Ordering

Alphabetic
By Inheritance

Inherited

SystemVerilogParserVisitor
ParseTreeVisitor
AnyRef
Any

Hide All
Show All

Visibility

Public
Protected

Abstract Value Members

abstract def visit(arg0: ParseTree): T
Definition Classes
ParseTreeVisitor
abstract def visitAction_block(ctx: Action_blockContext): T
Visit a parse tree produced by SystemVerilogParser#action_block.
Visit a parse tree produced by SystemVerilogParser#action_block.
ctx
the parse tree
returns
the visitor result
abstract def visitAlways_construct(ctx: Always_constructContext): T
Visit a parse tree produced by SystemVerilogParser#always_construct.
Visit a parse tree produced by SystemVerilogParser#always_construct.
ctx
the parse tree
returns
the visitor result
abstract def visitAlways_keyword(ctx: Always_keywordContext): T
Visit a parse tree produced by SystemVerilogParser#always_keyword.
Visit a parse tree produced by SystemVerilogParser#always_keyword.
ctx
the parse tree
returns
the visitor result
abstract def visitAnonymous_program(ctx: Anonymous_programContext): T
Visit a parse tree produced by SystemVerilogParser#anonymous_program.
Visit a parse tree produced by SystemVerilogParser#anonymous_program.
ctx
the parse tree
returns
the visitor result
abstract def visitAnonymous_program_item(ctx: Anonymous_program_itemContext): T
Visit a parse tree produced by SystemVerilogParser#anonymous_program_item.
Visit a parse tree produced by SystemVerilogParser#anonymous_program_item.
ctx
the parse tree
returns
the visitor result
abstract def visitAnsi_port_declaration(ctx: Ansi_port_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#ansi_port_declaration.
Visit a parse tree produced by SystemVerilogParser#ansi_port_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitArg_list(ctx: Arg_listContext): T
Visit a parse tree produced by SystemVerilogParser#arg_list.
Visit a parse tree produced by SystemVerilogParser#arg_list.
ctx
the parse tree
returns
the visitor result
abstract def visitArray_key_val_pair(ctx: Array_key_val_pairContext): T
Visit a parse tree produced by SystemVerilogParser#array_key_val_pair.
Visit a parse tree produced by SystemVerilogParser#array_key_val_pair.
ctx
the parse tree
returns
the visitor result
abstract def visitArray_manipulation_call(ctx: Array_manipulation_callContext): T
Visit a parse tree produced by SystemVerilogParser#array_manipulation_call.
Visit a parse tree produced by SystemVerilogParser#array_manipulation_call.
ctx
the parse tree
returns
the visitor result
abstract def visitArray_method_name(ctx: Array_method_nameContext): T
Visit a parse tree produced by SystemVerilogParser#array_method_name.
Visit a parse tree produced by SystemVerilogParser#array_method_name.
ctx
the parse tree
returns
the visitor result
abstract def visitArray_pattern_key(ctx: Array_pattern_keyContext): T
Visit a parse tree produced by SystemVerilogParser#array_pattern_key.
Visit a parse tree produced by SystemVerilogParser#array_pattern_key.
ctx
the parse tree
returns
the visitor result
abstract def visitArray_range_expression(ctx: Array_range_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#array_range_expression.
Visit a parse tree produced by SystemVerilogParser#array_range_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitAssert_property_statement(ctx: Assert_property_statementContext): T
Visit a parse tree produced by SystemVerilogParser#assert_property_statement.
Visit a parse tree produced by SystemVerilogParser#assert_property_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitAssertion_item(ctx: Assertion_itemContext): T
Visit a parse tree produced by SystemVerilogParser#assertion_item.
Visit a parse tree produced by SystemVerilogParser#assertion_item.
ctx
the parse tree
returns
the visitor result
abstract def visitAssertion_item_declaration(ctx: Assertion_item_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#assertion_item_declaration.
Visit a parse tree produced by SystemVerilogParser#assertion_item_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitAssertion_variable_declaration(ctx: Assertion_variable_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#assertion_variable_declaration.
Visit a parse tree produced by SystemVerilogParser#assertion_variable_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitAssignment_operator(ctx: Assignment_operatorContext): T
Visit a parse tree produced by SystemVerilogParser#assignment_operator.
Visit a parse tree produced by SystemVerilogParser#assignment_operator.
ctx
the parse tree
returns
the visitor result
abstract def visitAssignment_pattern(ctx: Assignment_patternContext): T
Visit a parse tree produced by SystemVerilogParser#assignment_pattern.
Visit a parse tree produced by SystemVerilogParser#assignment_pattern.
ctx
the parse tree
returns
the visitor result
abstract def visitAssignment_pattern_expression(ctx: Assignment_pattern_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_expression.
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitAssignment_pattern_expression_type(ctx: Assignment_pattern_expression_typeContext): T
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_expression_type.
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_expression_type.
ctx
the parse tree
returns
the visitor result
abstract def visitAssignment_pattern_key(ctx: Assignment_pattern_keyContext): T
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_key.
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_key.
ctx
the parse tree
returns
the visitor result
abstract def visitAssignment_pattern_net_lvalue(ctx: Assignment_pattern_net_lvalueContext): T
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_net_lvalue.
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_net_lvalue.
ctx
the parse tree
returns
the visitor result
abstract def visitAssignment_pattern_variable_lvalue(ctx: Assignment_pattern_variable_lvalueContext): T
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_variable_lvalue.
Visit a parse tree produced by SystemVerilogParser#assignment_pattern_variable_lvalue.
ctx
the parse tree
returns
the visitor result
abstract def visitAssociative_dimension(ctx: Associative_dimensionContext): T
Visit a parse tree produced by SystemVerilogParser#associative_dimension.
Visit a parse tree produced by SystemVerilogParser#associative_dimension.
ctx
the parse tree
returns
the visitor result
abstract def visitAssume_property_statement(ctx: Assume_property_statementContext): T
Visit a parse tree produced by SystemVerilogParser#assume_property_statement.
Visit a parse tree produced by SystemVerilogParser#assume_property_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitAttr_name(ctx: Attr_nameContext): T
Visit a parse tree produced by SystemVerilogParser#attr_name.
Visit a parse tree produced by SystemVerilogParser#attr_name.
ctx
the parse tree
returns
the visitor result
abstract def visitAttr_spec(ctx: Attr_specContext): T
Visit a parse tree produced by SystemVerilogParser#attr_spec.
Visit a parse tree produced by SystemVerilogParser#attr_spec.
ctx
the parse tree
returns
the visitor result
abstract def visitAttribute_instance(ctx: Attribute_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#attribute_instance.
Visit a parse tree produced by SystemVerilogParser#attribute_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitBin_array_size(ctx: Bin_array_sizeContext): T
Visit a parse tree produced by SystemVerilogParser#bin_array_size.
Visit a parse tree produced by SystemVerilogParser#bin_array_size.
ctx
the parse tree
returns
the visitor result
abstract def visitBin_identifier(ctx: Bin_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#bin_identifier.
Visit a parse tree produced by SystemVerilogParser#bin_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitBinary_base(ctx: Binary_baseContext): T
Visit a parse tree produced by SystemVerilogParser#binary_base.
Visit a parse tree produced by SystemVerilogParser#binary_base.
ctx
the parse tree
returns
the visitor result
abstract def visitBinary_number(ctx: Binary_numberContext): T
Visit a parse tree produced by SystemVerilogParser#binary_number.
Visit a parse tree produced by SystemVerilogParser#binary_number.
ctx
the parse tree
returns
the visitor result
abstract def visitBinary_value(ctx: Binary_valueContext): T
Visit a parse tree produced by SystemVerilogParser#binary_value.
Visit a parse tree produced by SystemVerilogParser#binary_value.
ctx
the parse tree
returns
the visitor result
abstract def visitBind_directive(ctx: Bind_directiveContext): T
Visit a parse tree produced by SystemVerilogParser#bind_directive.
Visit a parse tree produced by SystemVerilogParser#bind_directive.
ctx
the parse tree
returns
the visitor result
abstract def visitBind_instantiation(ctx: Bind_instantiationContext): T
Visit a parse tree produced by SystemVerilogParser#bind_instantiation.
Visit a parse tree produced by SystemVerilogParser#bind_instantiation.
ctx
the parse tree
returns
the visitor result
abstract def visitBind_target_instance(ctx: Bind_target_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#bind_target_instance.
Visit a parse tree produced by SystemVerilogParser#bind_target_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitBind_target_instance_list(ctx: Bind_target_instance_listContext): T
Visit a parse tree produced by SystemVerilogParser#bind_target_instance_list.
Visit a parse tree produced by SystemVerilogParser#bind_target_instance_list.
ctx
the parse tree
returns
the visitor result
abstract def visitBind_target_scope(ctx: Bind_target_scopeContext): T
Visit a parse tree produced by SystemVerilogParser#bind_target_scope.
Visit a parse tree produced by SystemVerilogParser#bind_target_scope.
ctx
the parse tree
returns
the visitor result
abstract def visitBins_expression(ctx: Bins_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#bins_expression.
Visit a parse tree produced by SystemVerilogParser#bins_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitBins_keyword(ctx: Bins_keywordContext): T
Visit a parse tree produced by SystemVerilogParser#bins_keyword.
Visit a parse tree produced by SystemVerilogParser#bins_keyword.
ctx
the parse tree
returns
the visitor result
abstract def visitBins_or_empty(ctx: Bins_or_emptyContext): T
Visit a parse tree produced by SystemVerilogParser#bins_or_empty.
Visit a parse tree produced by SystemVerilogParser#bins_or_empty.
ctx
the parse tree
returns
the visitor result
abstract def visitBins_or_options(ctx: Bins_or_optionsContext): T
Visit a parse tree produced by SystemVerilogParser#bins_or_options.
Visit a parse tree produced by SystemVerilogParser#bins_or_options.
ctx
the parse tree
returns
the visitor result
abstract def visitBins_selection(ctx: Bins_selectionContext): T
Visit a parse tree produced by SystemVerilogParser#bins_selection.
Visit a parse tree produced by SystemVerilogParser#bins_selection.
ctx
the parse tree
returns
the visitor result
abstract def visitBins_selection_or_option(ctx: Bins_selection_or_optionContext): T
Visit a parse tree produced by SystemVerilogParser#bins_selection_or_option.
Visit a parse tree produced by SystemVerilogParser#bins_selection_or_option.
ctx
the parse tree
returns
the visitor result
abstract def visitBit_select(ctx: Bit_selectContext): T
Visit a parse tree produced by SystemVerilogParser#bit_select.
Visit a parse tree produced by SystemVerilogParser#bit_select.
ctx
the parse tree
returns
the visitor result
abstract def visitBlock_event_expression(ctx: Block_event_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#block_event_expression.
Visit a parse tree produced by SystemVerilogParser#block_event_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitBlock_identifier(ctx: Block_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#block_identifier.
Visit a parse tree produced by SystemVerilogParser#block_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitBlock_item_declaration(ctx: Block_item_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#block_item_declaration.
Visit a parse tree produced by SystemVerilogParser#block_item_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitBlock_label(ctx: Block_labelContext): T
Visit a parse tree produced by SystemVerilogParser#block_label.
Visit a parse tree produced by SystemVerilogParser#block_label.
ctx
the parse tree
returns
the visitor result
abstract def visitBlock_name(ctx: Block_nameContext): T
Visit a parse tree produced by SystemVerilogParser#block_name.
Visit a parse tree produced by SystemVerilogParser#block_name.
ctx
the parse tree
returns
the visitor result
abstract def visitBlocking_assignment(ctx: Blocking_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#blocking_assignment.
Visit a parse tree produced by SystemVerilogParser#blocking_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitBoolean_abbrev(ctx: Boolean_abbrevContext): T
Visit a parse tree produced by SystemVerilogParser#boolean_abbrev.
Visit a parse tree produced by SystemVerilogParser#boolean_abbrev.
ctx
the parse tree
returns
the visitor result
abstract def visitC_identifier(ctx: C_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#c_identifier.
Visit a parse tree produced by SystemVerilogParser#c_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_body_1(ctx: Case_body_1Context): T
Visit a parse tree produced by SystemVerilogParser#case_body_1.
Visit a parse tree produced by SystemVerilogParser#case_body_1.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_body_2(ctx: Case_body_2Context): T
Visit a parse tree produced by SystemVerilogParser#case_body_2.
Visit a parse tree produced by SystemVerilogParser#case_body_2.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_body_3(ctx: Case_body_3Context): T
Visit a parse tree produced by SystemVerilogParser#case_body_3.
Visit a parse tree produced by SystemVerilogParser#case_body_3.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_expression(ctx: Case_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#case_expression.
Visit a parse tree produced by SystemVerilogParser#case_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_generate_construct(ctx: Case_generate_constructContext): T
Visit a parse tree produced by SystemVerilogParser#case_generate_construct.
Visit a parse tree produced by SystemVerilogParser#case_generate_construct.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_generate_item(ctx: Case_generate_itemContext): T
Visit a parse tree produced by SystemVerilogParser#case_generate_item.
Visit a parse tree produced by SystemVerilogParser#case_generate_item.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_inside_item(ctx: Case_inside_itemContext): T
Visit a parse tree produced by SystemVerilogParser#case_inside_item.
Visit a parse tree produced by SystemVerilogParser#case_inside_item.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_item(ctx: Case_itemContext): T
Visit a parse tree produced by SystemVerilogParser#case_item.
Visit a parse tree produced by SystemVerilogParser#case_item.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_item_expression(ctx: Case_item_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#case_item_expression.
Visit a parse tree produced by SystemVerilogParser#case_item_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_keyword(ctx: Case_keywordContext): T
Visit a parse tree produced by SystemVerilogParser#case_keyword.
Visit a parse tree produced by SystemVerilogParser#case_keyword.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_pattern_item(ctx: Case_pattern_itemContext): T
Visit a parse tree produced by SystemVerilogParser#case_pattern_item.
Visit a parse tree produced by SystemVerilogParser#case_pattern_item.
ctx
the parse tree
returns
the visitor result
abstract def visitCase_statement(ctx: Case_statementContext): T
Visit a parse tree produced by SystemVerilogParser#case_statement.
Visit a parse tree produced by SystemVerilogParser#case_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitCell_clause(ctx: Cell_clauseContext): T
Visit a parse tree produced by SystemVerilogParser#cell_clause.
Visit a parse tree produced by SystemVerilogParser#cell_clause.
ctx
the parse tree
returns
the visitor result
abstract def visitCell_identifier(ctx: Cell_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#cell_identifier.
Visit a parse tree produced by SystemVerilogParser#cell_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitCharge_strength(ctx: Charge_strengthContext): T
Visit a parse tree produced by SystemVerilogParser#charge_strength.
Visit a parse tree produced by SystemVerilogParser#charge_strength.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_decl_item(ctx: Checker_decl_itemContext): T
Visit a parse tree produced by SystemVerilogParser#checker_decl_item.
Visit a parse tree produced by SystemVerilogParser#checker_decl_item.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_declaration(ctx: Checker_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#checker_declaration.
Visit a parse tree produced by SystemVerilogParser#checker_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_identifier(ctx: Checker_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#checker_identifier.
Visit a parse tree produced by SystemVerilogParser#checker_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_instantiation(ctx: Checker_instantiationContext): T
Visit a parse tree produced by SystemVerilogParser#checker_instantiation.
Visit a parse tree produced by SystemVerilogParser#checker_instantiation.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_item(ctx: Checker_itemContext): T
Visit a parse tree produced by SystemVerilogParser#checker_item.
Visit a parse tree produced by SystemVerilogParser#checker_item.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_item_declaration(ctx: Checker_item_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#checker_item_declaration.
Visit a parse tree produced by SystemVerilogParser#checker_item_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_name(ctx: Checker_nameContext): T
Visit a parse tree produced by SystemVerilogParser#checker_name.
Visit a parse tree produced by SystemVerilogParser#checker_name.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_port_assign(ctx: Checker_port_assignContext): T
Visit a parse tree produced by SystemVerilogParser#checker_port_assign.
Visit a parse tree produced by SystemVerilogParser#checker_port_assign.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_port_direction(ctx: Checker_port_directionContext): T
Visit a parse tree produced by SystemVerilogParser#checker_port_direction.
Visit a parse tree produced by SystemVerilogParser#checker_port_direction.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_port_item(ctx: Checker_port_itemContext): T
Visit a parse tree produced by SystemVerilogParser#checker_port_item.
Visit a parse tree produced by SystemVerilogParser#checker_port_item.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_port_list(ctx: Checker_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#checker_port_list.
Visit a parse tree produced by SystemVerilogParser#checker_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitChecker_ports(ctx: Checker_portsContext): T
Visit a parse tree produced by SystemVerilogParser#checker_ports.
Visit a parse tree produced by SystemVerilogParser#checker_ports.
ctx
the parse tree
returns
the visitor result
abstract def visitChildren(arg0: RuleNode): T
Definition Classes
ParseTreeVisitor
abstract def visitClass_constraint(ctx: Class_constraintContext): T
Visit a parse tree produced by SystemVerilogParser#class_constraint.
Visit a parse tree produced by SystemVerilogParser#class_constraint.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_constructor_declaration(ctx: Class_constructor_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#class_constructor_declaration.
Visit a parse tree produced by SystemVerilogParser#class_constructor_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_constructor_prototype(ctx: Class_constructor_prototypeContext): T
Visit a parse tree produced by SystemVerilogParser#class_constructor_prototype.
Visit a parse tree produced by SystemVerilogParser#class_constructor_prototype.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_declaration(ctx: Class_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#class_declaration.
Visit a parse tree produced by SystemVerilogParser#class_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_extension(ctx: Class_extensionContext): T
Visit a parse tree produced by SystemVerilogParser#class_extension.
Visit a parse tree produced by SystemVerilogParser#class_extension.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_identifier(ctx: Class_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#class_identifier.
Visit a parse tree produced by SystemVerilogParser#class_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_implementation(ctx: Class_implementationContext): T
Visit a parse tree produced by SystemVerilogParser#class_implementation.
Visit a parse tree produced by SystemVerilogParser#class_implementation.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_item(ctx: Class_itemContext): T
Visit a parse tree produced by SystemVerilogParser#class_item.
Visit a parse tree produced by SystemVerilogParser#class_item.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_item_qualifier(ctx: Class_item_qualifierContext): T
Visit a parse tree produced by SystemVerilogParser#class_item_qualifier.
Visit a parse tree produced by SystemVerilogParser#class_item_qualifier.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_method(ctx: Class_methodContext): T
Visit a parse tree produced by SystemVerilogParser#class_method.
Visit a parse tree produced by SystemVerilogParser#class_method.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_name(ctx: Class_nameContext): T
Visit a parse tree produced by SystemVerilogParser#class_name.
Visit a parse tree produced by SystemVerilogParser#class_name.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_new(ctx: Class_newContext): T
Visit a parse tree produced by SystemVerilogParser#class_new.
Visit a parse tree produced by SystemVerilogParser#class_new.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_property(ctx: Class_propertyContext): T
Visit a parse tree produced by SystemVerilogParser#class_property.
Visit a parse tree produced by SystemVerilogParser#class_property.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_ref(ctx: Class_refContext): T
Visit a parse tree produced by SystemVerilogParser#class_ref.
Visit a parse tree produced by SystemVerilogParser#class_ref.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_scope(ctx: Class_scopeContext): T
Visit a parse tree produced by SystemVerilogParser#class_scope.
Visit a parse tree produced by SystemVerilogParser#class_scope.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_type(ctx: Class_typeContext): T
Visit a parse tree produced by SystemVerilogParser#class_type.
Visit a parse tree produced by SystemVerilogParser#class_type.
ctx
the parse tree
returns
the visitor result
abstract def visitClass_variable_identifier(ctx: Class_variable_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#class_variable_identifier.
Visit a parse tree produced by SystemVerilogParser#class_variable_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitClocking_decl_assign(ctx: Clocking_decl_assignContext): T
Visit a parse tree produced by SystemVerilogParser#clocking_decl_assign.
Visit a parse tree produced by SystemVerilogParser#clocking_decl_assign.
ctx
the parse tree
returns
the visitor result
abstract def visitClocking_declaration(ctx: Clocking_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#clocking_declaration.
Visit a parse tree produced by SystemVerilogParser#clocking_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitClocking_direction(ctx: Clocking_directionContext): T
Visit a parse tree produced by SystemVerilogParser#clocking_direction.
Visit a parse tree produced by SystemVerilogParser#clocking_direction.
ctx
the parse tree
returns
the visitor result
abstract def visitClocking_drive(ctx: Clocking_driveContext): T
Visit a parse tree produced by SystemVerilogParser#clocking_drive.
Visit a parse tree produced by SystemVerilogParser#clocking_drive.
ctx
the parse tree
returns
the visitor result
abstract def visitClocking_event(ctx: Clocking_eventContext): T
Visit a parse tree produced by SystemVerilogParser#clocking_event.
Visit a parse tree produced by SystemVerilogParser#clocking_event.
ctx
the parse tree
returns
the visitor result
abstract def visitClocking_identifier(ctx: Clocking_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#clocking_identifier.
Visit a parse tree produced by SystemVerilogParser#clocking_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitClocking_item(ctx: Clocking_itemContext): T
Visit a parse tree produced by SystemVerilogParser#clocking_item.
Visit a parse tree produced by SystemVerilogParser#clocking_item.
ctx
the parse tree
returns
the visitor result
abstract def visitClocking_name(ctx: Clocking_nameContext): T
Visit a parse tree produced by SystemVerilogParser#clocking_name.
Visit a parse tree produced by SystemVerilogParser#clocking_name.
ctx
the parse tree
returns
the visitor result
abstract def visitClocking_skew(ctx: Clocking_skewContext): T
Visit a parse tree produced by SystemVerilogParser#clocking_skew.
Visit a parse tree produced by SystemVerilogParser#clocking_skew.
ctx
the parse tree
returns
the visitor result
abstract def visitClockvar(ctx: ClockvarContext): T
Visit a parse tree produced by SystemVerilogParser#clockvar.
Visit a parse tree produced by SystemVerilogParser#clockvar.
ctx
the parse tree
returns
the visitor result
abstract def visitClockvar_expression(ctx: Clockvar_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#clockvar_expression.
Visit a parse tree produced by SystemVerilogParser#clockvar_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitCmos_switch_instance(ctx: Cmos_switch_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#cmos_switch_instance.
Visit a parse tree produced by SystemVerilogParser#cmos_switch_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitCmos_switchtype(ctx: Cmos_switchtypeContext): T
Visit a parse tree produced by SystemVerilogParser#cmos_switchtype.
Visit a parse tree produced by SystemVerilogParser#cmos_switchtype.
ctx
the parse tree
returns
the visitor result
abstract def visitCombinational_body(ctx: Combinational_bodyContext): T
Visit a parse tree produced by SystemVerilogParser#combinational_body.
Visit a parse tree produced by SystemVerilogParser#combinational_body.
ctx
the parse tree
returns
the visitor result
abstract def visitCombinational_entry(ctx: Combinational_entryContext): T
Visit a parse tree produced by SystemVerilogParser#combinational_entry.
Visit a parse tree produced by SystemVerilogParser#combinational_entry.
ctx
the parse tree
returns
the visitor result
abstract def visitConcatenation(ctx: ConcatenationContext): T
Visit a parse tree produced by SystemVerilogParser#concatenation.
Visit a parse tree produced by SystemVerilogParser#concatenation.
ctx
the parse tree
returns
the visitor result
abstract def visitConcurrent_assertion_item(ctx: Concurrent_assertion_itemContext): T
Visit a parse tree produced by SystemVerilogParser#concurrent_assertion_item.
Visit a parse tree produced by SystemVerilogParser#concurrent_assertion_item.
ctx
the parse tree
returns
the visitor result
abstract def visitConcurrent_assertion_statement(ctx: Concurrent_assertion_statementContext): T
Visit a parse tree produced by SystemVerilogParser#concurrent_assertion_statement.
Visit a parse tree produced by SystemVerilogParser#concurrent_assertion_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitCond_predicate(ctx: Cond_predicateContext): T
Visit a parse tree produced by SystemVerilogParser#cond_predicate.
Visit a parse tree produced by SystemVerilogParser#cond_predicate.
ctx
the parse tree
returns
the visitor result
abstract def visitConditional_generate_construct(ctx: Conditional_generate_constructContext): T
Visit a parse tree produced by SystemVerilogParser#conditional_generate_construct.
Visit a parse tree produced by SystemVerilogParser#conditional_generate_construct.
ctx
the parse tree
returns
the visitor result
abstract def visitConditional_statement(ctx: Conditional_statementContext): T
Visit a parse tree produced by SystemVerilogParser#conditional_statement.
Visit a parse tree produced by SystemVerilogParser#conditional_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitConditional_statement_body(ctx: Conditional_statement_bodyContext): T
Visit a parse tree produced by SystemVerilogParser#conditional_statement_body.
Visit a parse tree produced by SystemVerilogParser#conditional_statement_body.
ctx
the parse tree
returns
the visitor result
abstract def visitConditional_statement_chain(ctx: Conditional_statement_chainContext): T
Visit a parse tree produced by SystemVerilogParser#conditional_statement_chain.
Visit a parse tree produced by SystemVerilogParser#conditional_statement_chain.
ctx
the parse tree
returns
the visitor result
abstract def visitConditional_statement_else_chain(ctx: Conditional_statement_else_chainContext): T
Visit a parse tree produced by SystemVerilogParser#conditional_statement_else_chain.
Visit a parse tree produced by SystemVerilogParser#conditional_statement_else_chain.
ctx
the parse tree
returns
the visitor result
abstract def visitConditional_statement_else_tail(ctx: Conditional_statement_else_tailContext): T
Visit a parse tree produced by SystemVerilogParser#conditional_statement_else_tail.
Visit a parse tree produced by SystemVerilogParser#conditional_statement_else_tail.
ctx
the parse tree
returns
the visitor result
abstract def visitConditional_statement_head(ctx: Conditional_statement_headContext): T
Visit a parse tree produced by SystemVerilogParser#conditional_statement_head.
Visit a parse tree produced by SystemVerilogParser#conditional_statement_head.
ctx
the parse tree
returns
the visitor result
abstract def visitConfig_declaration(ctx: Config_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#config_declaration.
Visit a parse tree produced by SystemVerilogParser#config_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitConfig_identifier(ctx: Config_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#config_identifier.
Visit a parse tree produced by SystemVerilogParser#config_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitConfig_name(ctx: Config_nameContext): T
Visit a parse tree produced by SystemVerilogParser#config_name.
Visit a parse tree produced by SystemVerilogParser#config_name.
ctx
the parse tree
returns
the visitor result
abstract def visitConfig_rule_statement(ctx: Config_rule_statementContext): T
Visit a parse tree produced by SystemVerilogParser#config_rule_statement.
Visit a parse tree produced by SystemVerilogParser#config_rule_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitConsecutive_repetition(ctx: Consecutive_repetitionContext): T
Visit a parse tree produced by SystemVerilogParser#consecutive_repetition.
Visit a parse tree produced by SystemVerilogParser#consecutive_repetition.
ctx
the parse tree
returns
the visitor result
abstract def visitConst_identifier(ctx: Const_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#const_identifier.
Visit a parse tree produced by SystemVerilogParser#const_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitConst_member_select(ctx: Const_member_selectContext): T
Visit a parse tree produced by SystemVerilogParser#const_member_select.
Visit a parse tree produced by SystemVerilogParser#const_member_select.
ctx
the parse tree
returns
the visitor result
abstract def visitConst_or_range_expression(ctx: Const_or_range_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#const_or_range_expression.
Visit a parse tree produced by SystemVerilogParser#const_or_range_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_assignment_pattern_expression(ctx: Constant_assignment_pattern_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#constant_assignment_pattern_expression.
Visit a parse tree produced by SystemVerilogParser#constant_assignment_pattern_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_bit_select(ctx: Constant_bit_selectContext): T
Visit a parse tree produced by SystemVerilogParser#constant_bit_select.
Visit a parse tree produced by SystemVerilogParser#constant_bit_select.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_concatenation(ctx: Constant_concatenationContext): T
Visit a parse tree produced by SystemVerilogParser#constant_concatenation.
Visit a parse tree produced by SystemVerilogParser#constant_concatenation.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_expression(ctx: Constant_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#constant_expression.
Visit a parse tree produced by SystemVerilogParser#constant_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_indexed_range(ctx: Constant_indexed_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#constant_indexed_range.
Visit a parse tree produced by SystemVerilogParser#constant_indexed_range.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_mintypmax_expression(ctx: Constant_mintypmax_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#constant_mintypmax_expression.
Visit a parse tree produced by SystemVerilogParser#constant_mintypmax_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_multiple_concatenation(ctx: Constant_multiple_concatenationContext): T
Visit a parse tree produced by SystemVerilogParser#constant_multiple_concatenation.
Visit a parse tree produced by SystemVerilogParser#constant_multiple_concatenation.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_param_expression(ctx: Constant_param_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#constant_param_expression.
Visit a parse tree produced by SystemVerilogParser#constant_param_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_part_select_range(ctx: Constant_part_select_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#constant_part_select_range.
Visit a parse tree produced by SystemVerilogParser#constant_part_select_range.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_primary(ctx: Constant_primaryContext): T
Visit a parse tree produced by SystemVerilogParser#constant_primary.
Visit a parse tree produced by SystemVerilogParser#constant_primary.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_range(ctx: Constant_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#constant_range.
Visit a parse tree produced by SystemVerilogParser#constant_range.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_range_expression(ctx: Constant_range_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#constant_range_expression.
Visit a parse tree produced by SystemVerilogParser#constant_range_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitConstant_select(ctx: Constant_selectContext): T
Visit a parse tree produced by SystemVerilogParser#constant_select.
Visit a parse tree produced by SystemVerilogParser#constant_select.
ctx
the parse tree
returns
the visitor result
abstract def visitConstraint_block(ctx: Constraint_blockContext): T
Visit a parse tree produced by SystemVerilogParser#constraint_block.
Visit a parse tree produced by SystemVerilogParser#constraint_block.
ctx
the parse tree
returns
the visitor result
abstract def visitConstraint_block_item(ctx: Constraint_block_itemContext): T
Visit a parse tree produced by SystemVerilogParser#constraint_block_item.
Visit a parse tree produced by SystemVerilogParser#constraint_block_item.
ctx
the parse tree
returns
the visitor result
abstract def visitConstraint_declaration(ctx: Constraint_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#constraint_declaration.
Visit a parse tree produced by SystemVerilogParser#constraint_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitConstraint_expression(ctx: Constraint_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#constraint_expression.
Visit a parse tree produced by SystemVerilogParser#constraint_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitConstraint_identifier(ctx: Constraint_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#constraint_identifier.
Visit a parse tree produced by SystemVerilogParser#constraint_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitConstraint_primary(ctx: Constraint_primaryContext): T
Visit a parse tree produced by SystemVerilogParser#constraint_primary.
Visit a parse tree produced by SystemVerilogParser#constraint_primary.
ctx
the parse tree
returns
the visitor result
abstract def visitConstraint_prototype(ctx: Constraint_prototypeContext): T
Visit a parse tree produced by SystemVerilogParser#constraint_prototype.
Visit a parse tree produced by SystemVerilogParser#constraint_prototype.
ctx
the parse tree
returns
the visitor result
abstract def visitConstraint_prototype_qualifier(ctx: Constraint_prototype_qualifierContext): T
Visit a parse tree produced by SystemVerilogParser#constraint_prototype_qualifier.
Visit a parse tree produced by SystemVerilogParser#constraint_prototype_qualifier.
ctx
the parse tree
returns
the visitor result
abstract def visitConstraint_set(ctx: Constraint_setContext): T
Visit a parse tree produced by SystemVerilogParser#constraint_set.
Visit a parse tree produced by SystemVerilogParser#constraint_set.
ctx
the parse tree
returns
the visitor result
abstract def visitContinuous_assign(ctx: Continuous_assignContext): T
Visit a parse tree produced by SystemVerilogParser#continuous_assign.
Visit a parse tree produced by SystemVerilogParser#continuous_assign.
ctx
the parse tree
returns
the visitor result
abstract def visitControlled_reference_event(ctx: Controlled_reference_eventContext): T
Visit a parse tree produced by SystemVerilogParser#controlled_reference_event.
Visit a parse tree produced by SystemVerilogParser#controlled_reference_event.
ctx
the parse tree
returns
the visitor result
abstract def visitControlled_timing_check_event(ctx: Controlled_timing_check_eventContext): T
Visit a parse tree produced by SystemVerilogParser#controlled_timing_check_event.
Visit a parse tree produced by SystemVerilogParser#controlled_timing_check_event.
ctx
the parse tree
returns
the visitor result
abstract def visitCover_cross(ctx: Cover_crossContext): T
Visit a parse tree produced by SystemVerilogParser#cover_cross.
Visit a parse tree produced by SystemVerilogParser#cover_cross.
ctx
the parse tree
returns
the visitor result
abstract def visitCover_point(ctx: Cover_pointContext): T
Visit a parse tree produced by SystemVerilogParser#cover_point.
Visit a parse tree produced by SystemVerilogParser#cover_point.
ctx
the parse tree
returns
the visitor result
abstract def visitCover_point_identifier(ctx: Cover_point_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#cover_point_identifier.
Visit a parse tree produced by SystemVerilogParser#cover_point_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitCover_point_label(ctx: Cover_point_labelContext): T
Visit a parse tree produced by SystemVerilogParser#cover_point_label.
Visit a parse tree produced by SystemVerilogParser#cover_point_label.
ctx
the parse tree
returns
the visitor result
abstract def visitCover_property_statement(ctx: Cover_property_statementContext): T
Visit a parse tree produced by SystemVerilogParser#cover_property_statement.
Visit a parse tree produced by SystemVerilogParser#cover_property_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitCover_sequence_statement(ctx: Cover_sequence_statementContext): T
Visit a parse tree produced by SystemVerilogParser#cover_sequence_statement.
Visit a parse tree produced by SystemVerilogParser#cover_sequence_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitCoverage_event(ctx: Coverage_eventContext): T
Visit a parse tree produced by SystemVerilogParser#coverage_event.
Visit a parse tree produced by SystemVerilogParser#coverage_event.
ctx
the parse tree
returns
the visitor result
abstract def visitCoverage_option(ctx: Coverage_optionContext): T
Visit a parse tree produced by SystemVerilogParser#coverage_option.
Visit a parse tree produced by SystemVerilogParser#coverage_option.
ctx
the parse tree
returns
the visitor result
abstract def visitCoverage_spec(ctx: Coverage_specContext): T
Visit a parse tree produced by SystemVerilogParser#coverage_spec.
Visit a parse tree produced by SystemVerilogParser#coverage_spec.
ctx
the parse tree
returns
the visitor result
abstract def visitCoverage_spec_or_option(ctx: Coverage_spec_or_optionContext): T
Visit a parse tree produced by SystemVerilogParser#coverage_spec_or_option.
Visit a parse tree produced by SystemVerilogParser#coverage_spec_or_option.
ctx
the parse tree
returns
the visitor result
abstract def visitCovergroup_declaration(ctx: Covergroup_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#covergroup_declaration.
Visit a parse tree produced by SystemVerilogParser#covergroup_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitCovergroup_expression(ctx: Covergroup_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#covergroup_expression.
Visit a parse tree produced by SystemVerilogParser#covergroup_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitCovergroup_identifier(ctx: Covergroup_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#covergroup_identifier.
Visit a parse tree produced by SystemVerilogParser#covergroup_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitCovergroup_name(ctx: Covergroup_nameContext): T
Visit a parse tree produced by SystemVerilogParser#covergroup_name.
Visit a parse tree produced by SystemVerilogParser#covergroup_name.
ctx
the parse tree
returns
the visitor result
abstract def visitCovergroup_range_list(ctx: Covergroup_range_listContext): T
Visit a parse tree produced by SystemVerilogParser#covergroup_range_list.
Visit a parse tree produced by SystemVerilogParser#covergroup_range_list.
ctx
the parse tree
returns
the visitor result
abstract def visitCovergroup_value_range(ctx: Covergroup_value_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#covergroup_value_range.
Visit a parse tree produced by SystemVerilogParser#covergroup_value_range.
ctx
the parse tree
returns
the visitor result
abstract def visitCross_body(ctx: Cross_bodyContext): T
Visit a parse tree produced by SystemVerilogParser#cross_body.
Visit a parse tree produced by SystemVerilogParser#cross_body.
ctx
the parse tree
returns
the visitor result
abstract def visitCross_body_item(ctx: Cross_body_itemContext): T
Visit a parse tree produced by SystemVerilogParser#cross_body_item.
Visit a parse tree produced by SystemVerilogParser#cross_body_item.
ctx
the parse tree
returns
the visitor result
abstract def visitCross_identifier(ctx: Cross_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#cross_identifier.
Visit a parse tree produced by SystemVerilogParser#cross_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitCross_item(ctx: Cross_itemContext): T
Visit a parse tree produced by SystemVerilogParser#cross_item.
Visit a parse tree produced by SystemVerilogParser#cross_item.
ctx
the parse tree
returns
the visitor result
abstract def visitCross_label(ctx: Cross_labelContext): T
Visit a parse tree produced by SystemVerilogParser#cross_label.
Visit a parse tree produced by SystemVerilogParser#cross_label.
ctx
the parse tree
returns
the visitor result
abstract def visitCross_set_expression(ctx: Cross_set_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#cross_set_expression.
Visit a parse tree produced by SystemVerilogParser#cross_set_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitCurrent_state(ctx: Current_stateContext): T
Visit a parse tree produced by SystemVerilogParser#current_state.
Visit a parse tree produced by SystemVerilogParser#current_state.
ctx
the parse tree
returns
the visitor result
abstract def visitCycle_delay(ctx: Cycle_delayContext): T
Visit a parse tree produced by SystemVerilogParser#cycle_delay.
Visit a parse tree produced by SystemVerilogParser#cycle_delay.
ctx
the parse tree
returns
the visitor result
abstract def visitCycle_delay_const_range_expression(ctx: Cycle_delay_const_range_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#cycle_delay_const_range_expression.
Visit a parse tree produced by SystemVerilogParser#cycle_delay_const_range_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitCycle_delay_range(ctx: Cycle_delay_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#cycle_delay_range.
Visit a parse tree produced by SystemVerilogParser#cycle_delay_range.
ctx
the parse tree
returns
the visitor result
abstract def visitData_declaration(ctx: Data_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#data_declaration.
Visit a parse tree produced by SystemVerilogParser#data_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitData_event(ctx: Data_eventContext): T
Visit a parse tree produced by SystemVerilogParser#data_event.
Visit a parse tree produced by SystemVerilogParser#data_event.
ctx
the parse tree
returns
the visitor result
abstract def visitData_source_expression(ctx: Data_source_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#data_source_expression.
Visit a parse tree produced by SystemVerilogParser#data_source_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitData_type(ctx: Data_typeContext): T
Visit a parse tree produced by SystemVerilogParser#data_type.
Visit a parse tree produced by SystemVerilogParser#data_type.
ctx
the parse tree
returns
the visitor result
abstract def visitData_type_or_implicit(ctx: Data_type_or_implicitContext): T
Visit a parse tree produced by SystemVerilogParser#data_type_or_implicit.
Visit a parse tree produced by SystemVerilogParser#data_type_or_implicit.
ctx
the parse tree
returns
the visitor result
abstract def visitData_type_or_void(ctx: Data_type_or_voidContext): T
Visit a parse tree produced by SystemVerilogParser#data_type_or_void.
Visit a parse tree produced by SystemVerilogParser#data_type_or_void.
ctx
the parse tree
returns
the visitor result
abstract def visitDecimal_base(ctx: Decimal_baseContext): T
Visit a parse tree produced by SystemVerilogParser#decimal_base.
Visit a parse tree produced by SystemVerilogParser#decimal_base.
ctx
the parse tree
returns
the visitor result
abstract def visitDecimal_number(ctx: Decimal_numberContext): T
Visit a parse tree produced by SystemVerilogParser#decimal_number.
Visit a parse tree produced by SystemVerilogParser#decimal_number.
ctx
the parse tree
returns
the visitor result
abstract def visitDecimal_value(ctx: Decimal_valueContext): T
Visit a parse tree produced by SystemVerilogParser#decimal_value.
Visit a parse tree produced by SystemVerilogParser#decimal_value.
ctx
the parse tree
returns
the visitor result
abstract def visitDefault_clause(ctx: Default_clauseContext): T
Visit a parse tree produced by SystemVerilogParser#default_clause.
Visit a parse tree produced by SystemVerilogParser#default_clause.
ctx
the parse tree
returns
the visitor result
abstract def visitDefault_skew(ctx: Default_skewContext): T
Visit a parse tree produced by SystemVerilogParser#default_skew.
Visit a parse tree produced by SystemVerilogParser#default_skew.
ctx
the parse tree
returns
the visitor result
abstract def visitDeferred_immediate_assert_statement(ctx: Deferred_immediate_assert_statementContext): T
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_assert_statement.
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_assert_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitDeferred_immediate_assertion_item(ctx: Deferred_immediate_assertion_itemContext): T
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_assertion_item.
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_assertion_item.
ctx
the parse tree
returns
the visitor result
abstract def visitDeferred_immediate_assertion_statement(ctx: Deferred_immediate_assertion_statementContext): T
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_assertion_statement.
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_assertion_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitDeferred_immediate_assume_statement(ctx: Deferred_immediate_assume_statementContext): T
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_assume_statement.
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_assume_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitDeferred_immediate_cover_statement(ctx: Deferred_immediate_cover_statementContext): T
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_cover_statement.
Visit a parse tree produced by SystemVerilogParser#deferred_immediate_cover_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitDefparam_assignment(ctx: Defparam_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#defparam_assignment.
Visit a parse tree produced by SystemVerilogParser#defparam_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitDelay2(ctx: Delay2Context): T
Visit a parse tree produced by SystemVerilogParser#delay2.
Visit a parse tree produced by SystemVerilogParser#delay2.
ctx
the parse tree
returns
the visitor result
abstract def visitDelay3(ctx: Delay3Context): T
Visit a parse tree produced by SystemVerilogParser#delay3.
Visit a parse tree produced by SystemVerilogParser#delay3.
ctx
the parse tree
returns
the visitor result
abstract def visitDelay_control(ctx: Delay_controlContext): T
Visit a parse tree produced by SystemVerilogParser#delay_control.
Visit a parse tree produced by SystemVerilogParser#delay_control.
ctx
the parse tree
returns
the visitor result
abstract def visitDelay_or_event_control(ctx: Delay_or_event_controlContext): T
Visit a parse tree produced by SystemVerilogParser#delay_or_event_control.
Visit a parse tree produced by SystemVerilogParser#delay_or_event_control.
ctx
the parse tree
returns
the visitor result
abstract def visitDelay_value(ctx: Delay_valueContext): T
Visit a parse tree produced by SystemVerilogParser#delay_value.
Visit a parse tree produced by SystemVerilogParser#delay_value.
ctx
the parse tree
returns
the visitor result
abstract def visitDelayed_data(ctx: Delayed_dataContext): T
Visit a parse tree produced by SystemVerilogParser#delayed_data.
Visit a parse tree produced by SystemVerilogParser#delayed_data.
ctx
the parse tree
returns
the visitor result
abstract def visitDelayed_data_opt(ctx: Delayed_data_optContext): T
Visit a parse tree produced by SystemVerilogParser#delayed_data_opt.
Visit a parse tree produced by SystemVerilogParser#delayed_data_opt.
ctx
the parse tree
returns
the visitor result
abstract def visitDelayed_ref_opt(ctx: Delayed_ref_optContext): T
Visit a parse tree produced by SystemVerilogParser#delayed_ref_opt.
Visit a parse tree produced by SystemVerilogParser#delayed_ref_opt.
ctx
the parse tree
returns
the visitor result
abstract def visitDelayed_reference(ctx: Delayed_referenceContext): T
Visit a parse tree produced by SystemVerilogParser#delayed_reference.
Visit a parse tree produced by SystemVerilogParser#delayed_reference.
ctx
the parse tree
returns
the visitor result
abstract def visitDescription(ctx: DescriptionContext): T
Visit a parse tree produced by SystemVerilogParser#description.
Visit a parse tree produced by SystemVerilogParser#description.
ctx
the parse tree
returns
the visitor result
abstract def visitDesign_statement(ctx: Design_statementContext): T
Visit a parse tree produced by SystemVerilogParser#design_statement.
Visit a parse tree produced by SystemVerilogParser#design_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitDesign_statement_item(ctx: Design_statement_itemContext): T
Visit a parse tree produced by SystemVerilogParser#design_statement_item.
Visit a parse tree produced by SystemVerilogParser#design_statement_item.
ctx
the parse tree
returns
the visitor result
abstract def visitDisable_statement(ctx: Disable_statementContext): T
Visit a parse tree produced by SystemVerilogParser#disable_statement.
Visit a parse tree produced by SystemVerilogParser#disable_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitDist_item(ctx: Dist_itemContext): T
Visit a parse tree produced by SystemVerilogParser#dist_item.
Visit a parse tree produced by SystemVerilogParser#dist_item.
ctx
the parse tree
returns
the visitor result
abstract def visitDist_list(ctx: Dist_listContext): T
Visit a parse tree produced by SystemVerilogParser#dist_list.
Visit a parse tree produced by SystemVerilogParser#dist_list.
ctx
the parse tree
returns
the visitor result
abstract def visitDist_weight(ctx: Dist_weightContext): T
Visit a parse tree produced by SystemVerilogParser#dist_weight.
Visit a parse tree produced by SystemVerilogParser#dist_weight.
ctx
the parse tree
returns
the visitor result
abstract def visitDpi_function_import_property(ctx: Dpi_function_import_propertyContext): T
Visit a parse tree produced by SystemVerilogParser#dpi_function_import_property.
Visit a parse tree produced by SystemVerilogParser#dpi_function_import_property.
ctx
the parse tree
returns
the visitor result
abstract def visitDpi_function_proto(ctx: Dpi_function_protoContext): T
Visit a parse tree produced by SystemVerilogParser#dpi_function_proto.
Visit a parse tree produced by SystemVerilogParser#dpi_function_proto.
ctx
the parse tree
returns
the visitor result
abstract def visitDpi_import_export(ctx: Dpi_import_exportContext): T
Visit a parse tree produced by SystemVerilogParser#dpi_import_export.
Visit a parse tree produced by SystemVerilogParser#dpi_import_export.
ctx
the parse tree
returns
the visitor result
abstract def visitDpi_spec_string(ctx: Dpi_spec_stringContext): T
Visit a parse tree produced by SystemVerilogParser#dpi_spec_string.
Visit a parse tree produced by SystemVerilogParser#dpi_spec_string.
ctx
the parse tree
returns
the visitor result
abstract def visitDpi_task_import_property(ctx: Dpi_task_import_propertyContext): T
Visit a parse tree produced by SystemVerilogParser#dpi_task_import_property.
Visit a parse tree produced by SystemVerilogParser#dpi_task_import_property.
ctx
the parse tree
returns
the visitor result
abstract def visitDpi_task_proto(ctx: Dpi_task_protoContext): T
Visit a parse tree produced by SystemVerilogParser#dpi_task_proto.
Visit a parse tree produced by SystemVerilogParser#dpi_task_proto.
ctx
the parse tree
returns
the visitor result
abstract def visitDrive_strength(ctx: Drive_strengthContext): T
Visit a parse tree produced by SystemVerilogParser#drive_strength.
Visit a parse tree produced by SystemVerilogParser#drive_strength.
ctx
the parse tree
returns
the visitor result
abstract def visitDynamic_array_new(ctx: Dynamic_array_newContext): T
Visit a parse tree produced by SystemVerilogParser#dynamic_array_new.
Visit a parse tree produced by SystemVerilogParser#dynamic_array_new.
ctx
the parse tree
returns
the visitor result
abstract def visitDynamic_array_variable_identifier(ctx: Dynamic_array_variable_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#dynamic_array_variable_identifier.
Visit a parse tree produced by SystemVerilogParser#dynamic_array_variable_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitEdge_control_specifier(ctx: Edge_control_specifierContext): T
Visit a parse tree produced by SystemVerilogParser#edge_control_specifier.
Visit a parse tree produced by SystemVerilogParser#edge_control_specifier.
ctx
the parse tree
returns
the visitor result
abstract def visitEdge_descriptor(ctx: Edge_descriptorContext): T
Visit a parse tree produced by SystemVerilogParser#edge_descriptor.
Visit a parse tree produced by SystemVerilogParser#edge_descriptor.
ctx
the parse tree
returns
the visitor result
abstract def visitEdge_identifier(ctx: Edge_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#edge_identifier.
Visit a parse tree produced by SystemVerilogParser#edge_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitEdge_indicator(ctx: Edge_indicatorContext): T
Visit a parse tree produced by SystemVerilogParser#edge_indicator.
Visit a parse tree produced by SystemVerilogParser#edge_indicator.
ctx
the parse tree
returns
the visitor result
abstract def visitEdge_input_list(ctx: Edge_input_listContext): T
Visit a parse tree produced by SystemVerilogParser#edge_input_list.
Visit a parse tree produced by SystemVerilogParser#edge_input_list.
ctx
the parse tree
returns
the visitor result
abstract def visitEdge_sensitive_path_declaration(ctx: Edge_sensitive_path_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#edge_sensitive_path_declaration.
Visit a parse tree produced by SystemVerilogParser#edge_sensitive_path_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitEdge_symbol(ctx: Edge_symbolContext): T
Visit a parse tree produced by SystemVerilogParser#edge_symbol.
Visit a parse tree produced by SystemVerilogParser#edge_symbol.
ctx
the parse tree
returns
the visitor result
abstract def visitElaboration_system_task(ctx: Elaboration_system_taskContext): T
Visit a parse tree produced by SystemVerilogParser#elaboration_system_task.
Visit a parse tree produced by SystemVerilogParser#elaboration_system_task.
ctx
the parse tree
returns
the visitor result
abstract def visitEmpty_unpacked_array_concatenation(ctx: Empty_unpacked_array_concatenationContext): T
Visit a parse tree produced by SystemVerilogParser#empty_unpacked_array_concatenation.
Visit a parse tree produced by SystemVerilogParser#empty_unpacked_array_concatenation.
ctx
the parse tree
returns
the visitor result
abstract def visitEnable_gate_instance(ctx: Enable_gate_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#enable_gate_instance.
Visit a parse tree produced by SystemVerilogParser#enable_gate_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitEnable_gatetype(ctx: Enable_gatetypeContext): T
Visit a parse tree produced by SystemVerilogParser#enable_gatetype.
Visit a parse tree produced by SystemVerilogParser#enable_gatetype.
ctx
the parse tree
returns
the visitor result
abstract def visitEnable_terminal(ctx: Enable_terminalContext): T
Visit a parse tree produced by SystemVerilogParser#enable_terminal.
Visit a parse tree produced by SystemVerilogParser#enable_terminal.
ctx
the parse tree
returns
the visitor result
abstract def visitEnd_edge_offset(ctx: End_edge_offsetContext): T
Visit a parse tree produced by SystemVerilogParser#end_edge_offset.
Visit a parse tree produced by SystemVerilogParser#end_edge_offset.
ctx
the parse tree
returns
the visitor result
abstract def visitEnum_base_type(ctx: Enum_base_typeContext): T
Visit a parse tree produced by SystemVerilogParser#enum_base_type.
Visit a parse tree produced by SystemVerilogParser#enum_base_type.
ctx
the parse tree
returns
the visitor result
abstract def visitEnum_identifier(ctx: Enum_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#enum_identifier.
Visit a parse tree produced by SystemVerilogParser#enum_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitEnum_name_declaration(ctx: Enum_name_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#enum_name_declaration.
Visit a parse tree produced by SystemVerilogParser#enum_name_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitEnum_name_suffix_range(ctx: Enum_name_suffix_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#enum_name_suffix_range.
Visit a parse tree produced by SystemVerilogParser#enum_name_suffix_range.
ctx
the parse tree
returns
the visitor result
abstract def visitErrorNode(arg0: ErrorNode): T
Definition Classes
ParseTreeVisitor
abstract def visitError_limit_value(ctx: Error_limit_valueContext): T
Visit a parse tree produced by SystemVerilogParser#error_limit_value.
Visit a parse tree produced by SystemVerilogParser#error_limit_value.
ctx
the parse tree
returns
the visitor result
abstract def visitEscaped_identifier(ctx: Escaped_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#escaped_identifier.
Visit a parse tree produced by SystemVerilogParser#escaped_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitEvent_based_flag(ctx: Event_based_flagContext): T
Visit a parse tree produced by SystemVerilogParser#event_based_flag.
Visit a parse tree produced by SystemVerilogParser#event_based_flag.
ctx
the parse tree
returns
the visitor result
abstract def visitEvent_based_flag_opt(ctx: Event_based_flag_optContext): T
Visit a parse tree produced by SystemVerilogParser#event_based_flag_opt.
Visit a parse tree produced by SystemVerilogParser#event_based_flag_opt.
ctx
the parse tree
returns
the visitor result
abstract def visitEvent_control(ctx: Event_controlContext): T
Visit a parse tree produced by SystemVerilogParser#event_control.
Visit a parse tree produced by SystemVerilogParser#event_control.
ctx
the parse tree
returns
the visitor result
abstract def visitEvent_expression(ctx: Event_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#event_expression.
Visit a parse tree produced by SystemVerilogParser#event_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitEvent_trigger(ctx: Event_triggerContext): T
Visit a parse tree produced by SystemVerilogParser#event_trigger.
Visit a parse tree produced by SystemVerilogParser#event_trigger.
ctx
the parse tree
returns
the visitor result
abstract def visitExpect_property_statement(ctx: Expect_property_statementContext): T
Visit a parse tree produced by SystemVerilogParser#expect_property_statement.
Visit a parse tree produced by SystemVerilogParser#expect_property_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitExponential_number(ctx: Exponential_numberContext): T
Visit a parse tree produced by SystemVerilogParser#exponential_number.
Visit a parse tree produced by SystemVerilogParser#exponential_number.
ctx
the parse tree
returns
the visitor result
abstract def visitExpression(ctx: ExpressionContext): T
Visit a parse tree produced by SystemVerilogParser#expression.
Visit a parse tree produced by SystemVerilogParser#expression.
ctx
the parse tree
returns
the visitor result
abstract def visitExpression_or_cond_pattern(ctx: Expression_or_cond_patternContext): T
Visit a parse tree produced by SystemVerilogParser#expression_or_cond_pattern.
Visit a parse tree produced by SystemVerilogParser#expression_or_cond_pattern.
ctx
the parse tree
returns
the visitor result
abstract def visitExpression_or_dist(ctx: Expression_or_distContext): T
Visit a parse tree produced by SystemVerilogParser#expression_or_dist.
Visit a parse tree produced by SystemVerilogParser#expression_or_dist.
ctx
the parse tree
returns
the visitor result
abstract def visitExtern_constraint_declaration(ctx: Extern_constraint_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#extern_constraint_declaration.
Visit a parse tree produced by SystemVerilogParser#extern_constraint_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitExtern_tf_declaration(ctx: Extern_tf_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#extern_tf_declaration.
Visit a parse tree produced by SystemVerilogParser#extern_tf_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitFatal_arg_list(ctx: Fatal_arg_listContext): T
Visit a parse tree produced by SystemVerilogParser#fatal_arg_list.
Visit a parse tree produced by SystemVerilogParser#fatal_arg_list.
ctx
the parse tree
returns
the visitor result
abstract def visitFile_path_spec(ctx: File_path_specContext): T
Visit a parse tree produced by SystemVerilogParser#file_path_spec.
Visit a parse tree produced by SystemVerilogParser#file_path_spec.
ctx
the parse tree
returns
the visitor result
abstract def visitFinal_construct(ctx: Final_constructContext): T
Visit a parse tree produced by SystemVerilogParser#final_construct.
Visit a parse tree produced by SystemVerilogParser#final_construct.
ctx
the parse tree
returns
the visitor result
abstract def visitFinish_number(ctx: Finish_numberContext): T
Visit a parse tree produced by SystemVerilogParser#finish_number.
Visit a parse tree produced by SystemVerilogParser#finish_number.
ctx
the parse tree
returns
the visitor result
abstract def visitFixed_point_number(ctx: Fixed_point_numberContext): T
Visit a parse tree produced by SystemVerilogParser#fixed_point_number.
Visit a parse tree produced by SystemVerilogParser#fixed_point_number.
ctx
the parse tree
returns
the visitor result
abstract def visitFor_initialization(ctx: For_initializationContext): T
Visit a parse tree produced by SystemVerilogParser#for_initialization.
Visit a parse tree produced by SystemVerilogParser#for_initialization.
ctx
the parse tree
returns
the visitor result
abstract def visitFor_step(ctx: For_stepContext): T
Visit a parse tree produced by SystemVerilogParser#for_step.
Visit a parse tree produced by SystemVerilogParser#for_step.
ctx
the parse tree
returns
the visitor result
abstract def visitFor_step_assignment(ctx: For_step_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#for_step_assignment.
Visit a parse tree produced by SystemVerilogParser#for_step_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitFor_variable_assign(ctx: For_variable_assignContext): T
Visit a parse tree produced by SystemVerilogParser#for_variable_assign.
Visit a parse tree produced by SystemVerilogParser#for_variable_assign.
ctx
the parse tree
returns
the visitor result
abstract def visitFor_variable_declaration(ctx: For_variable_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#for_variable_declaration.
Visit a parse tree produced by SystemVerilogParser#for_variable_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitFormal_port_identifier(ctx: Formal_port_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#formal_port_identifier.
Visit a parse tree produced by SystemVerilogParser#formal_port_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitFull_edge_sensitive_path_description(ctx: Full_edge_sensitive_path_descriptionContext): T
Visit a parse tree produced by SystemVerilogParser#full_edge_sensitive_path_description.
Visit a parse tree produced by SystemVerilogParser#full_edge_sensitive_path_description.
ctx
the parse tree
returns
the visitor result
abstract def visitFull_path_description(ctx: Full_path_descriptionContext): T
Visit a parse tree produced by SystemVerilogParser#full_path_description.
Visit a parse tree produced by SystemVerilogParser#full_path_description.
ctx
the parse tree
returns
the visitor result
abstract def visitFullskew_timing_check(ctx: Fullskew_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#fullskew_timing_check.
Visit a parse tree produced by SystemVerilogParser#fullskew_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitFunction_body_declaration(ctx: Function_body_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#function_body_declaration.
Visit a parse tree produced by SystemVerilogParser#function_body_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitFunction_data_type_or_implicit(ctx: Function_data_type_or_implicitContext): T
Visit a parse tree produced by SystemVerilogParser#function_data_type_or_implicit.
Visit a parse tree produced by SystemVerilogParser#function_data_type_or_implicit.
ctx
the parse tree
returns
the visitor result
abstract def visitFunction_declaration(ctx: Function_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#function_declaration.
Visit a parse tree produced by SystemVerilogParser#function_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitFunction_identifier(ctx: Function_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#function_identifier.
Visit a parse tree produced by SystemVerilogParser#function_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitFunction_name(ctx: Function_nameContext): T
Visit a parse tree produced by SystemVerilogParser#function_name.
Visit a parse tree produced by SystemVerilogParser#function_name.
ctx
the parse tree
returns
the visitor result
abstract def visitFunction_prototype(ctx: Function_prototypeContext): T
Visit a parse tree produced by SystemVerilogParser#function_prototype.
Visit a parse tree produced by SystemVerilogParser#function_prototype.
ctx
the parse tree
returns
the visitor result
abstract def visitFunction_statement(ctx: Function_statementContext): T
Visit a parse tree produced by SystemVerilogParser#function_statement.
Visit a parse tree produced by SystemVerilogParser#function_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitFunction_statement_or_null(ctx: Function_statement_or_nullContext): T
Visit a parse tree produced by SystemVerilogParser#function_statement_or_null.
Visit a parse tree produced by SystemVerilogParser#function_statement_or_null.
ctx
the parse tree
returns
the visitor result
abstract def visitGate_instantiation(ctx: Gate_instantiationContext): T
Visit a parse tree produced by SystemVerilogParser#gate_instantiation.
Visit a parse tree produced by SystemVerilogParser#gate_instantiation.
ctx
the parse tree
returns
the visitor result
abstract def visitGen_ref(ctx: Gen_refContext): T
Visit a parse tree produced by SystemVerilogParser#gen_ref.
Visit a parse tree produced by SystemVerilogParser#gen_ref.
ctx
the parse tree
returns
the visitor result
abstract def visitGenerate_block(ctx: Generate_blockContext): T
Visit a parse tree produced by SystemVerilogParser#generate_block.
Visit a parse tree produced by SystemVerilogParser#generate_block.
ctx
the parse tree
returns
the visitor result
abstract def visitGenerate_block_identifier(ctx: Generate_block_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#generate_block_identifier.
Visit a parse tree produced by SystemVerilogParser#generate_block_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitGenerate_block_label(ctx: Generate_block_labelContext): T
Visit a parse tree produced by SystemVerilogParser#generate_block_label.
Visit a parse tree produced by SystemVerilogParser#generate_block_label.
ctx
the parse tree
returns
the visitor result
abstract def visitGenerate_block_name(ctx: Generate_block_nameContext): T
Visit a parse tree produced by SystemVerilogParser#generate_block_name.
Visit a parse tree produced by SystemVerilogParser#generate_block_name.
ctx
the parse tree
returns
the visitor result
abstract def visitGenerate_item(ctx: Generate_itemContext): T
Visit a parse tree produced by SystemVerilogParser#generate_item.
Visit a parse tree produced by SystemVerilogParser#generate_item.
ctx
the parse tree
returns
the visitor result
abstract def visitGenerate_region(ctx: Generate_regionContext): T
Visit a parse tree produced by SystemVerilogParser#generate_region.
Visit a parse tree produced by SystemVerilogParser#generate_region.
ctx
the parse tree
returns
the visitor result
abstract def visitGenvar_declaration(ctx: Genvar_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#genvar_declaration.
Visit a parse tree produced by SystemVerilogParser#genvar_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitGenvar_expression(ctx: Genvar_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#genvar_expression.
Visit a parse tree produced by SystemVerilogParser#genvar_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitGenvar_identifier(ctx: Genvar_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#genvar_identifier.
Visit a parse tree produced by SystemVerilogParser#genvar_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitGenvar_initialization(ctx: Genvar_initializationContext): T
Visit a parse tree produced by SystemVerilogParser#genvar_initialization.
Visit a parse tree produced by SystemVerilogParser#genvar_initialization.
ctx
the parse tree
returns
the visitor result
abstract def visitGenvar_iteration(ctx: Genvar_iterationContext): T
Visit a parse tree produced by SystemVerilogParser#genvar_iteration.
Visit a parse tree produced by SystemVerilogParser#genvar_iteration.
ctx
the parse tree
returns
the visitor result
abstract def visitGoto_repetition(ctx: Goto_repetitionContext): T
Visit a parse tree produced by SystemVerilogParser#goto_repetition.
Visit a parse tree produced by SystemVerilogParser#goto_repetition.
ctx
the parse tree
returns
the visitor result
abstract def visitHex_base(ctx: Hex_baseContext): T
Visit a parse tree produced by SystemVerilogParser#hex_base.
Visit a parse tree produced by SystemVerilogParser#hex_base.
ctx
the parse tree
returns
the visitor result
abstract def visitHex_number(ctx: Hex_numberContext): T
Visit a parse tree produced by SystemVerilogParser#hex_number.
Visit a parse tree produced by SystemVerilogParser#hex_number.
ctx
the parse tree
returns
the visitor result
abstract def visitHex_value(ctx: Hex_valueContext): T
Visit a parse tree produced by SystemVerilogParser#hex_value.
Visit a parse tree produced by SystemVerilogParser#hex_value.
ctx
the parse tree
returns
the visitor result
abstract def visitHier_ref(ctx: Hier_refContext): T
Visit a parse tree produced by SystemVerilogParser#hier_ref.
Visit a parse tree produced by SystemVerilogParser#hier_ref.
ctx
the parse tree
returns
the visitor result
abstract def visitHierarchical_btf_identifier(ctx: Hierarchical_btf_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#hierarchical_btf_identifier.
Visit a parse tree produced by SystemVerilogParser#hierarchical_btf_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitHierarchical_identifier(ctx: Hierarchical_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#hierarchical_identifier.
Visit a parse tree produced by SystemVerilogParser#hierarchical_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitHierarchical_instance(ctx: Hierarchical_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#hierarchical_instance.
Visit a parse tree produced by SystemVerilogParser#hierarchical_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitHold_timing_check(ctx: Hold_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#hold_timing_check.
Visit a parse tree produced by SystemVerilogParser#hold_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitId_list(ctx: Id_listContext): T
Visit a parse tree produced by SystemVerilogParser#id_list.
Visit a parse tree produced by SystemVerilogParser#id_list.
ctx
the parse tree
returns
the visitor result
abstract def visitIdentifier(ctx: IdentifierContext): T
Visit a parse tree produced by SystemVerilogParser#identifier.
Visit a parse tree produced by SystemVerilogParser#identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitIdentifier_list(ctx: Identifier_listContext): T
Visit a parse tree produced by SystemVerilogParser#identifier_list.
Visit a parse tree produced by SystemVerilogParser#identifier_list.
ctx
the parse tree
returns
the visitor result
abstract def visitIf_generate_construct(ctx: If_generate_constructContext): T
Visit a parse tree produced by SystemVerilogParser#if_generate_construct.
Visit a parse tree produced by SystemVerilogParser#if_generate_construct.
ctx
the parse tree
returns
the visitor result
abstract def visitImmediate_assertion_statement(ctx: Immediate_assertion_statementContext): T
Visit a parse tree produced by SystemVerilogParser#immediate_assertion_statement.
Visit a parse tree produced by SystemVerilogParser#immediate_assertion_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitImplicit_class_handle(ctx: Implicit_class_handleContext): T
Visit a parse tree produced by SystemVerilogParser#implicit_class_handle.
Visit a parse tree produced by SystemVerilogParser#implicit_class_handle.
ctx
the parse tree
returns
the visitor result
abstract def visitImplicit_data_type(ctx: Implicit_data_typeContext): T
Visit a parse tree produced by SystemVerilogParser#implicit_data_type.
Visit a parse tree produced by SystemVerilogParser#implicit_data_type.
ctx
the parse tree
returns
the visitor result
abstract def visitImport_export(ctx: Import_exportContext): T
Visit a parse tree produced by SystemVerilogParser#import_export.
Visit a parse tree produced by SystemVerilogParser#import_export.
ctx
the parse tree
returns
the visitor result
abstract def visitInc_or_dec_expression(ctx: Inc_or_dec_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#inc_or_dec_expression.
Visit a parse tree produced by SystemVerilogParser#inc_or_dec_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitInc_or_dec_operator(ctx: Inc_or_dec_operatorContext): T
Visit a parse tree produced by SystemVerilogParser#inc_or_dec_operator.
Visit a parse tree produced by SystemVerilogParser#inc_or_dec_operator.
ctx
the parse tree
returns
the visitor result
abstract def visitInclude_statement(ctx: Include_statementContext): T
Visit a parse tree produced by SystemVerilogParser#include_statement.
Visit a parse tree produced by SystemVerilogParser#include_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitIncomplete_condition_statement(ctx: Incomplete_condition_statementContext): T
Visit a parse tree produced by SystemVerilogParser#incomplete_condition_statement.
Visit a parse tree produced by SystemVerilogParser#incomplete_condition_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitIncomplete_statement(ctx: Incomplete_statementContext): T
Visit a parse tree produced by SystemVerilogParser#incomplete_statement.
Visit a parse tree produced by SystemVerilogParser#incomplete_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitIndex_variable_identifier(ctx: Index_variable_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#index_variable_identifier.
Visit a parse tree produced by SystemVerilogParser#index_variable_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitIndexed_range(ctx: Indexed_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#indexed_range.
Visit a parse tree produced by SystemVerilogParser#indexed_range.
ctx
the parse tree
returns
the visitor result
abstract def visitInit_val(ctx: Init_valContext): T
Visit a parse tree produced by SystemVerilogParser#init_val.
Visit a parse tree produced by SystemVerilogParser#init_val.
ctx
the parse tree
returns
the visitor result
abstract def visitInitial_construct(ctx: Initial_constructContext): T
Visit a parse tree produced by SystemVerilogParser#initial_construct.
Visit a parse tree produced by SystemVerilogParser#initial_construct.
ctx
the parse tree
returns
the visitor result
abstract def visitInout_declaration(ctx: Inout_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#inout_declaration.
Visit a parse tree produced by SystemVerilogParser#inout_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitInout_terminal(ctx: Inout_terminalContext): T
Visit a parse tree produced by SystemVerilogParser#inout_terminal.
Visit a parse tree produced by SystemVerilogParser#inout_terminal.
ctx
the parse tree
returns
the visitor result
abstract def visitInput_declaration(ctx: Input_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#input_declaration.
Visit a parse tree produced by SystemVerilogParser#input_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitInput_identifier(ctx: Input_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#input_identifier.
Visit a parse tree produced by SystemVerilogParser#input_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitInput_port_identifier(ctx: Input_port_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#input_port_identifier.
Visit a parse tree produced by SystemVerilogParser#input_port_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitInput_terminal(ctx: Input_terminalContext): T
Visit a parse tree produced by SystemVerilogParser#input_terminal.
Visit a parse tree produced by SystemVerilogParser#input_terminal.
ctx
the parse tree
returns
the visitor result
abstract def visitInst_clause(ctx: Inst_clauseContext): T
Visit a parse tree produced by SystemVerilogParser#inst_clause.
Visit a parse tree produced by SystemVerilogParser#inst_clause.
ctx
the parse tree
returns
the visitor result
abstract def visitInst_name(ctx: Inst_nameContext): T
Visit a parse tree produced by SystemVerilogParser#inst_name.
Visit a parse tree produced by SystemVerilogParser#inst_name.
ctx
the parse tree
returns
the visitor result
abstract def visitInstance_identifier(ctx: Instance_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#instance_identifier.
Visit a parse tree produced by SystemVerilogParser#instance_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitInteger_atom_type(ctx: Integer_atom_typeContext): T
Visit a parse tree produced by SystemVerilogParser#integer_atom_type.
Visit a parse tree produced by SystemVerilogParser#integer_atom_type.
ctx
the parse tree
returns
the visitor result
abstract def visitInteger_covergroup_expression(ctx: Integer_covergroup_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#integer_covergroup_expression.
Visit a parse tree produced by SystemVerilogParser#integer_covergroup_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitInteger_type(ctx: Integer_typeContext): T
Visit a parse tree produced by SystemVerilogParser#integer_type.
Visit a parse tree produced by SystemVerilogParser#integer_type.
ctx
the parse tree
returns
the visitor result
abstract def visitInteger_vector_type(ctx: Integer_vector_typeContext): T
Visit a parse tree produced by SystemVerilogParser#integer_vector_type.
Visit a parse tree produced by SystemVerilogParser#integer_vector_type.
ctx
the parse tree
returns
the visitor result
abstract def visitIntegral_number(ctx: Integral_numberContext): T
Visit a parse tree produced by SystemVerilogParser#integral_number.
Visit a parse tree produced by SystemVerilogParser#integral_number.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_class_declaration(ctx: Interface_class_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#interface_class_declaration.
Visit a parse tree produced by SystemVerilogParser#interface_class_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_class_extension(ctx: Interface_class_extensionContext): T
Visit a parse tree produced by SystemVerilogParser#interface_class_extension.
Visit a parse tree produced by SystemVerilogParser#interface_class_extension.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_class_item(ctx: Interface_class_itemContext): T
Visit a parse tree produced by SystemVerilogParser#interface_class_item.
Visit a parse tree produced by SystemVerilogParser#interface_class_item.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_class_method(ctx: Interface_class_methodContext): T
Visit a parse tree produced by SystemVerilogParser#interface_class_method.
Visit a parse tree produced by SystemVerilogParser#interface_class_method.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_class_type(ctx: Interface_class_typeContext): T
Visit a parse tree produced by SystemVerilogParser#interface_class_type.
Visit a parse tree produced by SystemVerilogParser#interface_class_type.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_declaration(ctx: Interface_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#interface_declaration.
Visit a parse tree produced by SystemVerilogParser#interface_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_header(ctx: Interface_headerContext): T
Visit a parse tree produced by SystemVerilogParser#interface_header.
Visit a parse tree produced by SystemVerilogParser#interface_header.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_id(ctx: Interface_idContext): T
Visit a parse tree produced by SystemVerilogParser#interface_id.
Visit a parse tree produced by SystemVerilogParser#interface_id.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_identifier(ctx: Interface_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#interface_identifier.
Visit a parse tree produced by SystemVerilogParser#interface_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_instance_identifier(ctx: Interface_instance_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#interface_instance_identifier.
Visit a parse tree produced by SystemVerilogParser#interface_instance_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_item(ctx: Interface_itemContext): T
Visit a parse tree produced by SystemVerilogParser#interface_item.
Visit a parse tree produced by SystemVerilogParser#interface_item.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_name(ctx: Interface_nameContext): T
Visit a parse tree produced by SystemVerilogParser#interface_name.
Visit a parse tree produced by SystemVerilogParser#interface_name.
ctx
the parse tree
returns
the visitor result
abstract def visitInterface_port_declaration(ctx: Interface_port_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#interface_port_declaration.
Visit a parse tree produced by SystemVerilogParser#interface_port_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitJoin_keyword(ctx: Join_keywordContext): T
Visit a parse tree produced by SystemVerilogParser#join_keyword.
Visit a parse tree produced by SystemVerilogParser#join_keyword.
ctx
the parse tree
returns
the visitor result
abstract def visitJump_statement(ctx: Jump_statementContext): T
Visit a parse tree produced by SystemVerilogParser#jump_statement.
Visit a parse tree produced by SystemVerilogParser#jump_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitLet_declaration(ctx: Let_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#let_declaration.
Visit a parse tree produced by SystemVerilogParser#let_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitLet_formal_type(ctx: Let_formal_typeContext): T
Visit a parse tree produced by SystemVerilogParser#let_formal_type.
Visit a parse tree produced by SystemVerilogParser#let_formal_type.
ctx
the parse tree
returns
the visitor result
abstract def visitLet_identifier(ctx: Let_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#let_identifier.
Visit a parse tree produced by SystemVerilogParser#let_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitLet_port_item(ctx: Let_port_itemContext): T
Visit a parse tree produced by SystemVerilogParser#let_port_item.
Visit a parse tree produced by SystemVerilogParser#let_port_item.
ctx
the parse tree
returns
the visitor result
abstract def visitLet_port_list(ctx: Let_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#let_port_list.
Visit a parse tree produced by SystemVerilogParser#let_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitLet_ports(ctx: Let_portsContext): T
Visit a parse tree produced by SystemVerilogParser#let_ports.
Visit a parse tree produced by SystemVerilogParser#let_ports.
ctx
the parse tree
returns
the visitor result
abstract def visitLevel_input_list(ctx: Level_input_listContext): T
Visit a parse tree produced by SystemVerilogParser#level_input_list.
Visit a parse tree produced by SystemVerilogParser#level_input_list.
ctx
the parse tree
returns
the visitor result
abstract def visitLevel_symbol(ctx: Level_symbolContext): T
Visit a parse tree produced by SystemVerilogParser#level_symbol.
Visit a parse tree produced by SystemVerilogParser#level_symbol.
ctx
the parse tree
returns
the visitor result
abstract def visitLiblist_clause(ctx: Liblist_clauseContext): T
Visit a parse tree produced by SystemVerilogParser#liblist_clause.
Visit a parse tree produced by SystemVerilogParser#liblist_clause.
ctx
the parse tree
returns
the visitor result
abstract def visitLibrary_declaration(ctx: Library_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#library_declaration.
Visit a parse tree produced by SystemVerilogParser#library_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitLibrary_description(ctx: Library_descriptionContext): T
Visit a parse tree produced by SystemVerilogParser#library_description.
Visit a parse tree produced by SystemVerilogParser#library_description.
ctx
the parse tree
returns
the visitor result
abstract def visitLibrary_identifier(ctx: Library_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#library_identifier.
Visit a parse tree produced by SystemVerilogParser#library_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitLibrary_incdir(ctx: Library_incdirContext): T
Visit a parse tree produced by SystemVerilogParser#library_incdir.
Visit a parse tree produced by SystemVerilogParser#library_incdir.
ctx
the parse tree
returns
the visitor result
abstract def visitLibrary_text(ctx: Library_textContext): T
Visit a parse tree produced by SystemVerilogParser#library_text.
Visit a parse tree produced by SystemVerilogParser#library_text.
ctx
the parse tree
returns
the visitor result
abstract def visitLifetime(ctx: LifetimeContext): T
Visit a parse tree produced by SystemVerilogParser#lifetime.
Visit a parse tree produced by SystemVerilogParser#lifetime.
ctx
the parse tree
returns
the visitor result
abstract def visitLimit_value(ctx: Limit_valueContext): T
Visit a parse tree produced by SystemVerilogParser#limit_value.
Visit a parse tree produced by SystemVerilogParser#limit_value.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_arguments(ctx: List_of_argumentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_arguments.
Visit a parse tree produced by SystemVerilogParser#list_of_arguments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_checker_port_connections(ctx: List_of_checker_port_connectionsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_checker_port_connections.
Visit a parse tree produced by SystemVerilogParser#list_of_checker_port_connections.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_clocking_decl_assign(ctx: List_of_clocking_decl_assignContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_clocking_decl_assign.
Visit a parse tree produced by SystemVerilogParser#list_of_clocking_decl_assign.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_cross_items(ctx: List_of_cross_itemsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_cross_items.
Visit a parse tree produced by SystemVerilogParser#list_of_cross_items.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_defparam_assignments(ctx: List_of_defparam_assignmentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_defparam_assignments.
Visit a parse tree produced by SystemVerilogParser#list_of_defparam_assignments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_genvar_identifiers(ctx: List_of_genvar_identifiersContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_genvar_identifiers.
Visit a parse tree produced by SystemVerilogParser#list_of_genvar_identifiers.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_interface_identifiers(ctx: List_of_interface_identifiersContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_interface_identifiers.
Visit a parse tree produced by SystemVerilogParser#list_of_interface_identifiers.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_net_assignments(ctx: List_of_net_assignmentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_net_assignments.
Visit a parse tree produced by SystemVerilogParser#list_of_net_assignments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_net_decl_assignments(ctx: List_of_net_decl_assignmentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_net_decl_assignments.
Visit a parse tree produced by SystemVerilogParser#list_of_net_decl_assignments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_param_assignments(ctx: List_of_param_assignmentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_param_assignments.
Visit a parse tree produced by SystemVerilogParser#list_of_param_assignments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_parameter_assignments(ctx: List_of_parameter_assignmentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_parameter_assignments.
Visit a parse tree produced by SystemVerilogParser#list_of_parameter_assignments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_path_delay_expressions(ctx: List_of_path_delay_expressionsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_path_delay_expressions.
Visit a parse tree produced by SystemVerilogParser#list_of_path_delay_expressions.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_path_inputs(ctx: List_of_path_inputsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_path_inputs.
Visit a parse tree produced by SystemVerilogParser#list_of_path_inputs.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_path_outputs(ctx: List_of_path_outputsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_path_outputs.
Visit a parse tree produced by SystemVerilogParser#list_of_path_outputs.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_port_connections(ctx: List_of_port_connectionsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_port_connections.
Visit a parse tree produced by SystemVerilogParser#list_of_port_connections.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_port_declarations(ctx: List_of_port_declarationsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_port_declarations.
Visit a parse tree produced by SystemVerilogParser#list_of_port_declarations.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_port_identifiers(ctx: List_of_port_identifiersContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_port_identifiers.
Visit a parse tree produced by SystemVerilogParser#list_of_port_identifiers.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_specparam_assignments(ctx: List_of_specparam_assignmentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_specparam_assignments.
Visit a parse tree produced by SystemVerilogParser#list_of_specparam_assignments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_tf_variable_identifiers(ctx: List_of_tf_variable_identifiersContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_tf_variable_identifiers.
Visit a parse tree produced by SystemVerilogParser#list_of_tf_variable_identifiers.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_type_assignments(ctx: List_of_type_assignmentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_type_assignments.
Visit a parse tree produced by SystemVerilogParser#list_of_type_assignments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_udp_port_identifiers(ctx: List_of_udp_port_identifiersContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_udp_port_identifiers.
Visit a parse tree produced by SystemVerilogParser#list_of_udp_port_identifiers.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_variable_assignments(ctx: List_of_variable_assignmentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_variable_assignments.
Visit a parse tree produced by SystemVerilogParser#list_of_variable_assignments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_variable_decl_assignments(ctx: List_of_variable_decl_assignmentsContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_variable_decl_assignments.
Visit a parse tree produced by SystemVerilogParser#list_of_variable_decl_assignments.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_variable_identifiers(ctx: List_of_variable_identifiersContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_variable_identifiers.
Visit a parse tree produced by SystemVerilogParser#list_of_variable_identifiers.
ctx
the parse tree
returns
the visitor result
abstract def visitList_of_variable_port_identifiers(ctx: List_of_variable_port_identifiersContext): T
Visit a parse tree produced by SystemVerilogParser#list_of_variable_port_identifiers.
Visit a parse tree produced by SystemVerilogParser#list_of_variable_port_identifiers.
ctx
the parse tree
returns
the visitor result
abstract def visitLocal_parameter_declaration(ctx: Local_parameter_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#local_parameter_declaration.
Visit a parse tree produced by SystemVerilogParser#local_parameter_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitLoop_generate_construct(ctx: Loop_generate_constructContext): T
Visit a parse tree produced by SystemVerilogParser#loop_generate_construct.
Visit a parse tree produced by SystemVerilogParser#loop_generate_construct.
ctx
the parse tree
returns
the visitor result
abstract def visitLoop_statement(ctx: Loop_statementContext): T
Visit a parse tree produced by SystemVerilogParser#loop_statement.
Visit a parse tree produced by SystemVerilogParser#loop_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitLoop_var(ctx: Loop_varContext): T
Visit a parse tree produced by SystemVerilogParser#loop_var.
Visit a parse tree produced by SystemVerilogParser#loop_var.
ctx
the parse tree
returns
the visitor result
abstract def visitLoop_variables(ctx: Loop_variablesContext): T
Visit a parse tree produced by SystemVerilogParser#loop_variables.
Visit a parse tree produced by SystemVerilogParser#loop_variables.
ctx
the parse tree
returns
the visitor result
abstract def visitMember_identifier(ctx: Member_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#member_identifier.
Visit a parse tree produced by SystemVerilogParser#member_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitMember_pattern_pair(ctx: Member_pattern_pairContext): T
Visit a parse tree produced by SystemVerilogParser#member_pattern_pair.
Visit a parse tree produced by SystemVerilogParser#member_pattern_pair.
ctx
the parse tree
returns
the visitor result
abstract def visitMember_select(ctx: Member_selectContext): T
Visit a parse tree produced by SystemVerilogParser#member_select.
Visit a parse tree produced by SystemVerilogParser#member_select.
ctx
the parse tree
returns
the visitor result
abstract def visitMethod_call_root(ctx: Method_call_rootContext): T
Visit a parse tree produced by SystemVerilogParser#method_call_root.
Visit a parse tree produced by SystemVerilogParser#method_call_root.
ctx
the parse tree
returns
the visitor result
abstract def visitMethod_identifier(ctx: Method_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#method_identifier.
Visit a parse tree produced by SystemVerilogParser#method_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitMethod_prototype(ctx: Method_prototypeContext): T
Visit a parse tree produced by SystemVerilogParser#method_prototype.
Visit a parse tree produced by SystemVerilogParser#method_prototype.
ctx
the parse tree
returns
the visitor result
abstract def visitMethod_qualifier(ctx: Method_qualifierContext): T
Visit a parse tree produced by SystemVerilogParser#method_qualifier.
Visit a parse tree produced by SystemVerilogParser#method_qualifier.
ctx
the parse tree
returns
the visitor result
abstract def visitMintypmax_expression(ctx: Mintypmax_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#mintypmax_expression.
Visit a parse tree produced by SystemVerilogParser#mintypmax_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitModport_clocking_declaration(ctx: Modport_clocking_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#modport_clocking_declaration.
Visit a parse tree produced by SystemVerilogParser#modport_clocking_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitModport_declaration(ctx: Modport_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#modport_declaration.
Visit a parse tree produced by SystemVerilogParser#modport_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitModport_identifier(ctx: Modport_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#modport_identifier.
Visit a parse tree produced by SystemVerilogParser#modport_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitModport_item(ctx: Modport_itemContext): T
Visit a parse tree produced by SystemVerilogParser#modport_item.
Visit a parse tree produced by SystemVerilogParser#modport_item.
ctx
the parse tree
returns
the visitor result
abstract def visitModport_ports_declaration(ctx: Modport_ports_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#modport_ports_declaration.
Visit a parse tree produced by SystemVerilogParser#modport_ports_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitModport_simple_port(ctx: Modport_simple_portContext): T
Visit a parse tree produced by SystemVerilogParser#modport_simple_port.
Visit a parse tree produced by SystemVerilogParser#modport_simple_port.
ctx
the parse tree
returns
the visitor result
abstract def visitModport_simple_ports_declaration(ctx: Modport_simple_ports_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#modport_simple_ports_declaration.
Visit a parse tree produced by SystemVerilogParser#modport_simple_ports_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitModport_tf_port(ctx: Modport_tf_portContext): T
Visit a parse tree produced by SystemVerilogParser#modport_tf_port.
Visit a parse tree produced by SystemVerilogParser#modport_tf_port.
ctx
the parse tree
returns
the visitor result
abstract def visitModport_tf_ports_declaration(ctx: Modport_tf_ports_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#modport_tf_ports_declaration.
Visit a parse tree produced by SystemVerilogParser#modport_tf_ports_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_common_item(ctx: Module_common_itemContext): T
Visit a parse tree produced by SystemVerilogParser#module_common_item.
Visit a parse tree produced by SystemVerilogParser#module_common_item.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_declaration(ctx: Module_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#module_declaration.
Visit a parse tree produced by SystemVerilogParser#module_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_header(ctx: Module_headerContext): T
Visit a parse tree produced by SystemVerilogParser#module_header.
Visit a parse tree produced by SystemVerilogParser#module_header.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_identifier(ctx: Module_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#module_identifier.
Visit a parse tree produced by SystemVerilogParser#module_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_item(ctx: Module_itemContext): T
Visit a parse tree produced by SystemVerilogParser#module_item.
Visit a parse tree produced by SystemVerilogParser#module_item.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_item_declaration(ctx: Module_item_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#module_item_declaration.
Visit a parse tree produced by SystemVerilogParser#module_item_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_keyword(ctx: Module_keywordContext): T
Visit a parse tree produced by SystemVerilogParser#module_keyword.
Visit a parse tree produced by SystemVerilogParser#module_keyword.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_name(ctx: Module_nameContext): T
Visit a parse tree produced by SystemVerilogParser#module_name.
Visit a parse tree produced by SystemVerilogParser#module_name.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_path_concatenation(ctx: Module_path_concatenationContext): T
Visit a parse tree produced by SystemVerilogParser#module_path_concatenation.
Visit a parse tree produced by SystemVerilogParser#module_path_concatenation.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_path_expression(ctx: Module_path_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#module_path_expression.
Visit a parse tree produced by SystemVerilogParser#module_path_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_path_mintypmax_expression(ctx: Module_path_mintypmax_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#module_path_mintypmax_expression.
Visit a parse tree produced by SystemVerilogParser#module_path_mintypmax_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_path_multiple_concatenation(ctx: Module_path_multiple_concatenationContext): T
Visit a parse tree produced by SystemVerilogParser#module_path_multiple_concatenation.
Visit a parse tree produced by SystemVerilogParser#module_path_multiple_concatenation.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_path_primary(ctx: Module_path_primaryContext): T
Visit a parse tree produced by SystemVerilogParser#module_path_primary.
Visit a parse tree produced by SystemVerilogParser#module_path_primary.
ctx
the parse tree
returns
the visitor result
abstract def visitModule_program_interface_instantiation(ctx: Module_program_interface_instantiationContext): T
Visit a parse tree produced by SystemVerilogParser#module_program_interface_instantiation.
Visit a parse tree produced by SystemVerilogParser#module_program_interface_instantiation.
ctx
the parse tree
returns
the visitor result
abstract def visitMos_switch_instance(ctx: Mos_switch_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#mos_switch_instance.
Visit a parse tree produced by SystemVerilogParser#mos_switch_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitMos_switchtype(ctx: Mos_switchtypeContext): T
Visit a parse tree produced by SystemVerilogParser#mos_switchtype.
Visit a parse tree produced by SystemVerilogParser#mos_switchtype.
ctx
the parse tree
returns
the visitor result
abstract def visitMultiple_concatenation(ctx: Multiple_concatenationContext): T
Visit a parse tree produced by SystemVerilogParser#multiple_concatenation.
Visit a parse tree produced by SystemVerilogParser#multiple_concatenation.
ctx
the parse tree
returns
the visitor result
abstract def visitN_input_gate_instance(ctx: N_input_gate_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#n_input_gate_instance.
Visit a parse tree produced by SystemVerilogParser#n_input_gate_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitN_input_gatetype(ctx: N_input_gatetypeContext): T
Visit a parse tree produced by SystemVerilogParser#n_input_gatetype.
Visit a parse tree produced by SystemVerilogParser#n_input_gatetype.
ctx
the parse tree
returns
the visitor result
abstract def visitN_output_gate_instance(ctx: N_output_gate_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#n_output_gate_instance.
Visit a parse tree produced by SystemVerilogParser#n_output_gate_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitN_output_gatetype(ctx: N_output_gatetypeContext): T
Visit a parse tree produced by SystemVerilogParser#n_output_gatetype.
Visit a parse tree produced by SystemVerilogParser#n_output_gatetype.
ctx
the parse tree
returns
the visitor result
abstract def visitName_of_instance(ctx: Name_of_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#name_of_instance.
Visit a parse tree produced by SystemVerilogParser#name_of_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitNamed_arg(ctx: Named_argContext): T
Visit a parse tree produced by SystemVerilogParser#named_arg.
Visit a parse tree produced by SystemVerilogParser#named_arg.
ctx
the parse tree
returns
the visitor result
abstract def visitNamed_checker_port_connection(ctx: Named_checker_port_connectionContext): T
Visit a parse tree produced by SystemVerilogParser#named_checker_port_connection.
Visit a parse tree produced by SystemVerilogParser#named_checker_port_connection.
ctx
the parse tree
returns
the visitor result
abstract def visitNamed_parameter_assignment(ctx: Named_parameter_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#named_parameter_assignment.
Visit a parse tree produced by SystemVerilogParser#named_parameter_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitNamed_port_connection(ctx: Named_port_connectionContext): T
Visit a parse tree produced by SystemVerilogParser#named_port_connection.
Visit a parse tree produced by SystemVerilogParser#named_port_connection.
ctx
the parse tree
returns
the visitor result
abstract def visitNcontrol_terminal(ctx: Ncontrol_terminalContext): T
Visit a parse tree produced by SystemVerilogParser#ncontrol_terminal.
Visit a parse tree produced by SystemVerilogParser#ncontrol_terminal.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_alias(ctx: Net_aliasContext): T
Visit a parse tree produced by SystemVerilogParser#net_alias.
Visit a parse tree produced by SystemVerilogParser#net_alias.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_assignment(ctx: Net_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#net_assignment.
Visit a parse tree produced by SystemVerilogParser#net_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_decl_assignment(ctx: Net_decl_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#net_decl_assignment.
Visit a parse tree produced by SystemVerilogParser#net_decl_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_declaration(ctx: Net_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#net_declaration.
Visit a parse tree produced by SystemVerilogParser#net_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_id(ctx: Net_idContext): T
Visit a parse tree produced by SystemVerilogParser#net_id.
Visit a parse tree produced by SystemVerilogParser#net_id.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_identifier(ctx: Net_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#net_identifier.
Visit a parse tree produced by SystemVerilogParser#net_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_lvalue(ctx: Net_lvalueContext): T
Visit a parse tree produced by SystemVerilogParser#net_lvalue.
Visit a parse tree produced by SystemVerilogParser#net_lvalue.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_port_type(ctx: Net_port_typeContext): T
Visit a parse tree produced by SystemVerilogParser#net_port_type.
Visit a parse tree produced by SystemVerilogParser#net_port_type.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_type(ctx: Net_typeContext): T
Visit a parse tree produced by SystemVerilogParser#net_type.
Visit a parse tree produced by SystemVerilogParser#net_type.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_type_decl_with(ctx: Net_type_decl_withContext): T
Visit a parse tree produced by SystemVerilogParser#net_type_decl_with.
Visit a parse tree produced by SystemVerilogParser#net_type_decl_with.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_type_declaration(ctx: Net_type_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#net_type_declaration.
Visit a parse tree produced by SystemVerilogParser#net_type_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitNet_type_identifier(ctx: Net_type_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#net_type_identifier.
Visit a parse tree produced by SystemVerilogParser#net_type_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitNext_state(ctx: Next_stateContext): T
Visit a parse tree produced by SystemVerilogParser#next_state.
Visit a parse tree produced by SystemVerilogParser#next_state.
ctx
the parse tree
returns
the visitor result
abstract def visitNochange_timing_check(ctx: Nochange_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#nochange_timing_check.
Visit a parse tree produced by SystemVerilogParser#nochange_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitNon_consecutive_repetition(ctx: Non_consecutive_repetitionContext): T
Visit a parse tree produced by SystemVerilogParser#non_consecutive_repetition.
Visit a parse tree produced by SystemVerilogParser#non_consecutive_repetition.
ctx
the parse tree
returns
the visitor result
abstract def visitNon_integer_type(ctx: Non_integer_typeContext): T
Visit a parse tree produced by SystemVerilogParser#non_integer_type.
Visit a parse tree produced by SystemVerilogParser#non_integer_type.
ctx
the parse tree
returns
the visitor result
abstract def visitNonblocking_assignment(ctx: Nonblocking_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#nonblocking_assignment.
Visit a parse tree produced by SystemVerilogParser#nonblocking_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitNonrange_select(ctx: Nonrange_selectContext): T
Visit a parse tree produced by SystemVerilogParser#nonrange_select.
Visit a parse tree produced by SystemVerilogParser#nonrange_select.
ctx
the parse tree
returns
the visitor result
abstract def visitNonrange_variable_lvalue(ctx: Nonrange_variable_lvalueContext): T
Visit a parse tree produced by SystemVerilogParser#nonrange_variable_lvalue.
Visit a parse tree produced by SystemVerilogParser#nonrange_variable_lvalue.
ctx
the parse tree
returns
the visitor result
abstract def visitNotifier(ctx: NotifierContext): T
Visit a parse tree produced by SystemVerilogParser#notifier.
Visit a parse tree produced by SystemVerilogParser#notifier.
ctx
the parse tree
returns
the visitor result
abstract def visitNotifier_opt(ctx: Notifier_optContext): T
Visit a parse tree produced by SystemVerilogParser#notifier_opt.
Visit a parse tree produced by SystemVerilogParser#notifier_opt.
ctx
the parse tree
returns
the visitor result
abstract def visitNumber(ctx: NumberContext): T
Visit a parse tree produced by SystemVerilogParser#number.
Visit a parse tree produced by SystemVerilogParser#number.
ctx
the parse tree
returns
the visitor result
abstract def visitOctal_base(ctx: Octal_baseContext): T
Visit a parse tree produced by SystemVerilogParser#octal_base.
Visit a parse tree produced by SystemVerilogParser#octal_base.
ctx
the parse tree
returns
the visitor result
abstract def visitOctal_number(ctx: Octal_numberContext): T
Visit a parse tree produced by SystemVerilogParser#octal_number.
Visit a parse tree produced by SystemVerilogParser#octal_number.
ctx
the parse tree
returns
the visitor result
abstract def visitOctal_value(ctx: Octal_valueContext): T
Visit a parse tree produced by SystemVerilogParser#octal_value.
Visit a parse tree produced by SystemVerilogParser#octal_value.
ctx
the parse tree
returns
the visitor result
abstract def visitOpen_range_list(ctx: Open_range_listContext): T
Visit a parse tree produced by SystemVerilogParser#open_range_list.
Visit a parse tree produced by SystemVerilogParser#open_range_list.
ctx
the parse tree
returns
the visitor result
abstract def visitOpen_value_range(ctx: Open_value_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#open_value_range.
Visit a parse tree produced by SystemVerilogParser#open_value_range.
ctx
the parse tree
returns
the visitor result
abstract def visitOperator_assignment(ctx: Operator_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#operator_assignment.
Visit a parse tree produced by SystemVerilogParser#operator_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitOrdered_arg(ctx: Ordered_argContext): T
Visit a parse tree produced by SystemVerilogParser#ordered_arg.
Visit a parse tree produced by SystemVerilogParser#ordered_arg.
ctx
the parse tree
returns
the visitor result
abstract def visitOrdered_checker_port_connection(ctx: Ordered_checker_port_connectionContext): T
Visit a parse tree produced by SystemVerilogParser#ordered_checker_port_connection.
Visit a parse tree produced by SystemVerilogParser#ordered_checker_port_connection.
ctx
the parse tree
returns
the visitor result
abstract def visitOrdered_parameter_assignment(ctx: Ordered_parameter_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#ordered_parameter_assignment.
Visit a parse tree produced by SystemVerilogParser#ordered_parameter_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitOrdered_port_connection(ctx: Ordered_port_connectionContext): T
Visit a parse tree produced by SystemVerilogParser#ordered_port_connection.
Visit a parse tree produced by SystemVerilogParser#ordered_port_connection.
ctx
the parse tree
returns
the visitor result
abstract def visitOutput_declaration(ctx: Output_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#output_declaration.
Visit a parse tree produced by SystemVerilogParser#output_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitOutput_identifier(ctx: Output_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#output_identifier.
Visit a parse tree produced by SystemVerilogParser#output_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitOutput_port_identifier(ctx: Output_port_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#output_port_identifier.
Visit a parse tree produced by SystemVerilogParser#output_port_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitOutput_symbol(ctx: Output_symbolContext): T
Visit a parse tree produced by SystemVerilogParser#output_symbol.
Visit a parse tree produced by SystemVerilogParser#output_symbol.
ctx
the parse tree
returns
the visitor result
abstract def visitOutput_terminal(ctx: Output_terminalContext): T
Visit a parse tree produced by SystemVerilogParser#output_terminal.
Visit a parse tree produced by SystemVerilogParser#output_terminal.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_declaration(ctx: Package_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#package_declaration.
Visit a parse tree produced by SystemVerilogParser#package_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_export_declaration(ctx: Package_export_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#package_export_declaration.
Visit a parse tree produced by SystemVerilogParser#package_export_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_identifier(ctx: Package_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#package_identifier.
Visit a parse tree produced by SystemVerilogParser#package_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_import_declaration(ctx: Package_import_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#package_import_declaration.
Visit a parse tree produced by SystemVerilogParser#package_import_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_import_item(ctx: Package_import_itemContext): T
Visit a parse tree produced by SystemVerilogParser#package_import_item.
Visit a parse tree produced by SystemVerilogParser#package_import_item.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_item(ctx: Package_itemContext): T
Visit a parse tree produced by SystemVerilogParser#package_item.
Visit a parse tree produced by SystemVerilogParser#package_item.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_item_declaration(ctx: Package_item_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#package_item_declaration.
Visit a parse tree produced by SystemVerilogParser#package_item_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_name(ctx: Package_nameContext): T
Visit a parse tree produced by SystemVerilogParser#package_name.
Visit a parse tree produced by SystemVerilogParser#package_name.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_or_class_scope(ctx: Package_or_class_scopeContext): T
Visit a parse tree produced by SystemVerilogParser#package_or_class_scope.
Visit a parse tree produced by SystemVerilogParser#package_or_class_scope.
ctx
the parse tree
returns
the visitor result
abstract def visitPackage_scope(ctx: Package_scopeContext): T
Visit a parse tree produced by SystemVerilogParser#package_scope.
Visit a parse tree produced by SystemVerilogParser#package_scope.
ctx
the parse tree
returns
the visitor result
abstract def visitPacked_dimension(ctx: Packed_dimensionContext): T
Visit a parse tree produced by SystemVerilogParser#packed_dimension.
Visit a parse tree produced by SystemVerilogParser#packed_dimension.
ctx
the parse tree
returns
the visitor result
abstract def visitPar_block(ctx: Par_blockContext): T
Visit a parse tree produced by SystemVerilogParser#par_block.
Visit a parse tree produced by SystemVerilogParser#par_block.
ctx
the parse tree
returns
the visitor result
abstract def visitParallel_edge_sensitive_path_description(ctx: Parallel_edge_sensitive_path_descriptionContext): T
Visit a parse tree produced by SystemVerilogParser#parallel_edge_sensitive_path_description.
Visit a parse tree produced by SystemVerilogParser#parallel_edge_sensitive_path_description.
ctx
the parse tree
returns
the visitor result
abstract def visitParallel_path_description(ctx: Parallel_path_descriptionContext): T
Visit a parse tree produced by SystemVerilogParser#parallel_path_description.
Visit a parse tree produced by SystemVerilogParser#parallel_path_description.
ctx
the parse tree
returns
the visitor result
abstract def visitParam_assignment(ctx: Param_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#param_assignment.
Visit a parse tree produced by SystemVerilogParser#param_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitParam_expression(ctx: Param_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#param_expression.
Visit a parse tree produced by SystemVerilogParser#param_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitParameter_declaration(ctx: Parameter_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#parameter_declaration.
Visit a parse tree produced by SystemVerilogParser#parameter_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitParameter_identifier(ctx: Parameter_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#parameter_identifier.
Visit a parse tree produced by SystemVerilogParser#parameter_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitParameter_override(ctx: Parameter_overrideContext): T
Visit a parse tree produced by SystemVerilogParser#parameter_override.
Visit a parse tree produced by SystemVerilogParser#parameter_override.
ctx
the parse tree
returns
the visitor result
abstract def visitParameter_port_declaration(ctx: Parameter_port_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#parameter_port_declaration.
Visit a parse tree produced by SystemVerilogParser#parameter_port_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitParameter_port_list(ctx: Parameter_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#parameter_port_list.
Visit a parse tree produced by SystemVerilogParser#parameter_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitParameter_value_assignment(ctx: Parameter_value_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#parameter_value_assignment.
Visit a parse tree produced by SystemVerilogParser#parameter_value_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitPart_select_range(ctx: Part_select_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#part_select_range.
Visit a parse tree produced by SystemVerilogParser#part_select_range.
ctx
the parse tree
returns
the visitor result
abstract def visitPass_en_switchtype(ctx: Pass_en_switchtypeContext): T
Visit a parse tree produced by SystemVerilogParser#pass_en_switchtype.
Visit a parse tree produced by SystemVerilogParser#pass_en_switchtype.
ctx
the parse tree
returns
the visitor result
abstract def visitPass_enable_switch_instance(ctx: Pass_enable_switch_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#pass_enable_switch_instance.
Visit a parse tree produced by SystemVerilogParser#pass_enable_switch_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitPass_switch_instance(ctx: Pass_switch_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#pass_switch_instance.
Visit a parse tree produced by SystemVerilogParser#pass_switch_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitPass_switchtype(ctx: Pass_switchtypeContext): T
Visit a parse tree produced by SystemVerilogParser#pass_switchtype.
Visit a parse tree produced by SystemVerilogParser#pass_switchtype.
ctx
the parse tree
returns
the visitor result
abstract def visitPath_declaration(ctx: Path_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#path_declaration.
Visit a parse tree produced by SystemVerilogParser#path_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitPath_delay_expression(ctx: Path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitPath_delay_value(ctx: Path_delay_valueContext): T
Visit a parse tree produced by SystemVerilogParser#path_delay_value.
Visit a parse tree produced by SystemVerilogParser#path_delay_value.
ctx
the parse tree
returns
the visitor result
abstract def visitPattern(ctx: PatternContext): T
Visit a parse tree produced by SystemVerilogParser#pattern.
Visit a parse tree produced by SystemVerilogParser#pattern.
ctx
the parse tree
returns
the visitor result
abstract def visitPcontrol_terminal(ctx: Pcontrol_terminalContext): T
Visit a parse tree produced by SystemVerilogParser#pcontrol_terminal.
Visit a parse tree produced by SystemVerilogParser#pcontrol_terminal.
ctx
the parse tree
returns
the visitor result
abstract def visitPeriod_timing_check(ctx: Period_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#period_timing_check.
Visit a parse tree produced by SystemVerilogParser#period_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitPkg_decl_item(ctx: Pkg_decl_itemContext): T
Visit a parse tree produced by SystemVerilogParser#pkg_decl_item.
Visit a parse tree produced by SystemVerilogParser#pkg_decl_item.
ctx
the parse tree
returns
the visitor result
abstract def visitPolarity_operator(ctx: Polarity_operatorContext): T
Visit a parse tree produced by SystemVerilogParser#polarity_operator.
Visit a parse tree produced by SystemVerilogParser#polarity_operator.
ctx
the parse tree
returns
the visitor result
abstract def visitPort(ctx: PortContext): T
Visit a parse tree produced by SystemVerilogParser#port.
Visit a parse tree produced by SystemVerilogParser#port.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_assign(ctx: Port_assignContext): T
Visit a parse tree produced by SystemVerilogParser#port_assign.
Visit a parse tree produced by SystemVerilogParser#port_assign.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_decl(ctx: Port_declContext): T
Visit a parse tree produced by SystemVerilogParser#port_decl.
Visit a parse tree produced by SystemVerilogParser#port_decl.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_declaration(ctx: Port_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#port_declaration.
Visit a parse tree produced by SystemVerilogParser#port_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_direction(ctx: Port_directionContext): T
Visit a parse tree produced by SystemVerilogParser#port_direction.
Visit a parse tree produced by SystemVerilogParser#port_direction.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_expression(ctx: Port_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#port_expression.
Visit a parse tree produced by SystemVerilogParser#port_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_id(ctx: Port_idContext): T
Visit a parse tree produced by SystemVerilogParser#port_id.
Visit a parse tree produced by SystemVerilogParser#port_id.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_identifier(ctx: Port_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#port_identifier.
Visit a parse tree produced by SystemVerilogParser#port_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_implicit(ctx: Port_implicitContext): T
Visit a parse tree produced by SystemVerilogParser#port_implicit.
Visit a parse tree produced by SystemVerilogParser#port_implicit.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_list(ctx: Port_listContext): T
Visit a parse tree produced by SystemVerilogParser#port_list.
Visit a parse tree produced by SystemVerilogParser#port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitPort_reference(ctx: Port_referenceContext): T
Visit a parse tree produced by SystemVerilogParser#port_reference.
Visit a parse tree produced by SystemVerilogParser#port_reference.
ctx
the parse tree
returns
the visitor result
abstract def visitPrimary(ctx: PrimaryContext): T
Visit a parse tree produced by SystemVerilogParser#primary.
Visit a parse tree produced by SystemVerilogParser#primary.
ctx
the parse tree
returns
the visitor result
abstract def visitPrimary_literal(ctx: Primary_literalContext): T
Visit a parse tree produced by SystemVerilogParser#primary_literal.
Visit a parse tree produced by SystemVerilogParser#primary_literal.
ctx
the parse tree
returns
the visitor result
abstract def visitProcedural_assertion_statement(ctx: Procedural_assertion_statementContext): T
Visit a parse tree produced by SystemVerilogParser#procedural_assertion_statement.
Visit a parse tree produced by SystemVerilogParser#procedural_assertion_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitProcedural_continuous_assignment(ctx: Procedural_continuous_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#procedural_continuous_assignment.
Visit a parse tree produced by SystemVerilogParser#procedural_continuous_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitProcedural_timing_control(ctx: Procedural_timing_controlContext): T
Visit a parse tree produced by SystemVerilogParser#procedural_timing_control.
Visit a parse tree produced by SystemVerilogParser#procedural_timing_control.
ctx
the parse tree
returns
the visitor result
abstract def visitProcedural_timing_control_statement(ctx: Procedural_timing_control_statementContext): T
Visit a parse tree produced by SystemVerilogParser#procedural_timing_control_statement.
Visit a parse tree produced by SystemVerilogParser#procedural_timing_control_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitProduction(ctx: ProductionContext): T
Visit a parse tree produced by SystemVerilogParser#production.
Visit a parse tree produced by SystemVerilogParser#production.
ctx
the parse tree
returns
the visitor result
abstract def visitProduction_identifier(ctx: Production_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#production_identifier.
Visit a parse tree produced by SystemVerilogParser#production_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitProduction_item(ctx: Production_itemContext): T
Visit a parse tree produced by SystemVerilogParser#production_item.
Visit a parse tree produced by SystemVerilogParser#production_item.
ctx
the parse tree
returns
the visitor result
abstract def visitProgram_declaration(ctx: Program_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#program_declaration.
Visit a parse tree produced by SystemVerilogParser#program_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitProgram_header(ctx: Program_headerContext): T
Visit a parse tree produced by SystemVerilogParser#program_header.
Visit a parse tree produced by SystemVerilogParser#program_header.
ctx
the parse tree
returns
the visitor result
abstract def visitProgram_identifier(ctx: Program_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#program_identifier.
Visit a parse tree produced by SystemVerilogParser#program_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitProgram_item(ctx: Program_itemContext): T
Visit a parse tree produced by SystemVerilogParser#program_item.
Visit a parse tree produced by SystemVerilogParser#program_item.
ctx
the parse tree
returns
the visitor result
abstract def visitProgram_name(ctx: Program_nameContext): T
Visit a parse tree produced by SystemVerilogParser#program_name.
Visit a parse tree produced by SystemVerilogParser#program_name.
ctx
the parse tree
returns
the visitor result
abstract def visitProp_arg_list(ctx: Prop_arg_listContext): T
Visit a parse tree produced by SystemVerilogParser#prop_arg_list.
Visit a parse tree produced by SystemVerilogParser#prop_arg_list.
ctx
the parse tree
returns
the visitor result
abstract def visitProp_named_arg(ctx: Prop_named_argContext): T
Visit a parse tree produced by SystemVerilogParser#prop_named_arg.
Visit a parse tree produced by SystemVerilogParser#prop_named_arg.
ctx
the parse tree
returns
the visitor result
abstract def visitProp_ordered_arg(ctx: Prop_ordered_argContext): T
Visit a parse tree produced by SystemVerilogParser#prop_ordered_arg.
Visit a parse tree produced by SystemVerilogParser#prop_ordered_arg.
ctx
the parse tree
returns
the visitor result
abstract def visitProp_port_item_local(ctx: Prop_port_item_localContext): T
Visit a parse tree produced by SystemVerilogParser#prop_port_item_local.
Visit a parse tree produced by SystemVerilogParser#prop_port_item_local.
ctx
the parse tree
returns
the visitor result
abstract def visitProp_port_list(ctx: Prop_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#prop_port_list.
Visit a parse tree produced by SystemVerilogParser#prop_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_actual_arg(ctx: Property_actual_argContext): T
Visit a parse tree produced by SystemVerilogParser#property_actual_arg.
Visit a parse tree produced by SystemVerilogParser#property_actual_arg.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_case_item(ctx: Property_case_itemContext): T
Visit a parse tree produced by SystemVerilogParser#property_case_item.
Visit a parse tree produced by SystemVerilogParser#property_case_item.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_declaration(ctx: Property_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#property_declaration.
Visit a parse tree produced by SystemVerilogParser#property_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_expr(ctx: Property_exprContext): T
Visit a parse tree produced by SystemVerilogParser#property_expr.
Visit a parse tree produced by SystemVerilogParser#property_expr.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_formal_type(ctx: Property_formal_typeContext): T
Visit a parse tree produced by SystemVerilogParser#property_formal_type.
Visit a parse tree produced by SystemVerilogParser#property_formal_type.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_identifier(ctx: Property_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#property_identifier.
Visit a parse tree produced by SystemVerilogParser#property_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_instance(ctx: Property_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#property_instance.
Visit a parse tree produced by SystemVerilogParser#property_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_list_of_arguments(ctx: Property_list_of_argumentsContext): T
Visit a parse tree produced by SystemVerilogParser#property_list_of_arguments.
Visit a parse tree produced by SystemVerilogParser#property_list_of_arguments.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_lvar_port_direction(ctx: Property_lvar_port_directionContext): T
Visit a parse tree produced by SystemVerilogParser#property_lvar_port_direction.
Visit a parse tree produced by SystemVerilogParser#property_lvar_port_direction.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_name(ctx: Property_nameContext): T
Visit a parse tree produced by SystemVerilogParser#property_name.
Visit a parse tree produced by SystemVerilogParser#property_name.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_port_item(ctx: Property_port_itemContext): T
Visit a parse tree produced by SystemVerilogParser#property_port_item.
Visit a parse tree produced by SystemVerilogParser#property_port_item.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_port_list(ctx: Property_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#property_port_list.
Visit a parse tree produced by SystemVerilogParser#property_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_qualifier(ctx: Property_qualifierContext): T
Visit a parse tree produced by SystemVerilogParser#property_qualifier.
Visit a parse tree produced by SystemVerilogParser#property_qualifier.
ctx
the parse tree
returns
the visitor result
abstract def visitProperty_spec(ctx: Property_specContext): T
Visit a parse tree produced by SystemVerilogParser#property_spec.
Visit a parse tree produced by SystemVerilogParser#property_spec.
ctx
the parse tree
returns
the visitor result
abstract def visitPs_identifier(ctx: Ps_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#ps_identifier.
Visit a parse tree produced by SystemVerilogParser#ps_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitPs_or_hierarchical_array_identifier(ctx: Ps_or_hierarchical_array_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#ps_or_hierarchical_array_identifier.
Visit a parse tree produced by SystemVerilogParser#ps_or_hierarchical_array_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitPs_or_hierarchical_identifier(ctx: Ps_or_hierarchical_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#ps_or_hierarchical_identifier.
Visit a parse tree produced by SystemVerilogParser#ps_or_hierarchical_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitPs_type_or_parameter_identifier(ctx: Ps_type_or_parameter_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#ps_type_or_parameter_identifier.
Visit a parse tree produced by SystemVerilogParser#ps_type_or_parameter_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitPull_gate_instance(ctx: Pull_gate_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#pull_gate_instance.
Visit a parse tree produced by SystemVerilogParser#pull_gate_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitPulldown_strength(ctx: Pulldown_strengthContext): T
Visit a parse tree produced by SystemVerilogParser#pulldown_strength.
Visit a parse tree produced by SystemVerilogParser#pulldown_strength.
ctx
the parse tree
returns
the visitor result
abstract def visitPullup_strength(ctx: Pullup_strengthContext): T
Visit a parse tree produced by SystemVerilogParser#pullup_strength.
Visit a parse tree produced by SystemVerilogParser#pullup_strength.
ctx
the parse tree
returns
the visitor result
abstract def visitPulse_control_specparam(ctx: Pulse_control_specparamContext): T
Visit a parse tree produced by SystemVerilogParser#pulse_control_specparam.
Visit a parse tree produced by SystemVerilogParser#pulse_control_specparam.
ctx
the parse tree
returns
the visitor result
abstract def visitPulsestyle_declaration(ctx: Pulsestyle_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#pulsestyle_declaration.
Visit a parse tree produced by SystemVerilogParser#pulsestyle_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitQueue_dimension(ctx: Queue_dimensionContext): T
Visit a parse tree produced by SystemVerilogParser#queue_dimension.
Visit a parse tree produced by SystemVerilogParser#queue_dimension.
ctx
the parse tree
returns
the visitor result
abstract def visitRand_list(ctx: Rand_listContext): T
Visit a parse tree produced by SystemVerilogParser#rand_list.
Visit a parse tree produced by SystemVerilogParser#rand_list.
ctx
the parse tree
returns
the visitor result
abstract def visitRand_with(ctx: Rand_withContext): T
Visit a parse tree produced by SystemVerilogParser#rand_with.
Visit a parse tree produced by SystemVerilogParser#rand_with.
ctx
the parse tree
returns
the visitor result
abstract def visitRandcase_item(ctx: Randcase_itemContext): T
Visit a parse tree produced by SystemVerilogParser#randcase_item.
Visit a parse tree produced by SystemVerilogParser#randcase_item.
ctx
the parse tree
returns
the visitor result
abstract def visitRandcase_statement(ctx: Randcase_statementContext): T
Visit a parse tree produced by SystemVerilogParser#randcase_statement.
Visit a parse tree produced by SystemVerilogParser#randcase_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitRandom_qualifier(ctx: Random_qualifierContext): T
Visit a parse tree produced by SystemVerilogParser#random_qualifier.
Visit a parse tree produced by SystemVerilogParser#random_qualifier.
ctx
the parse tree
returns
the visitor result
abstract def visitRandomize_call(ctx: Randomize_callContext): T
Visit a parse tree produced by SystemVerilogParser#randomize_call.
Visit a parse tree produced by SystemVerilogParser#randomize_call.
ctx
the parse tree
returns
the visitor result
abstract def visitRandsequence_statement(ctx: Randsequence_statementContext): T
Visit a parse tree produced by SystemVerilogParser#randsequence_statement.
Visit a parse tree produced by SystemVerilogParser#randsequence_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitRange_expression(ctx: Range_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#range_expression.
Visit a parse tree produced by SystemVerilogParser#range_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitReal_number(ctx: Real_numberContext): T
Visit a parse tree produced by SystemVerilogParser#real_number.
Visit a parse tree produced by SystemVerilogParser#real_number.
ctx
the parse tree
returns
the visitor result
abstract def visitRecovery_timing_check(ctx: Recovery_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#recovery_timing_check.
Visit a parse tree produced by SystemVerilogParser#recovery_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitRecrem_timing_check(ctx: Recrem_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#recrem_timing_check.
Visit a parse tree produced by SystemVerilogParser#recrem_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitRef_declaration(ctx: Ref_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#ref_declaration.
Visit a parse tree produced by SystemVerilogParser#ref_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitReference_event(ctx: Reference_eventContext): T
Visit a parse tree produced by SystemVerilogParser#reference_event.
Visit a parse tree produced by SystemVerilogParser#reference_event.
ctx
the parse tree
returns
the visitor result
abstract def visitReject_limit_value(ctx: Reject_limit_valueContext): T
Visit a parse tree produced by SystemVerilogParser#reject_limit_value.
Visit a parse tree produced by SystemVerilogParser#reject_limit_value.
ctx
the parse tree
returns
the visitor result
abstract def visitRemain_active_flag(ctx: Remain_active_flagContext): T
Visit a parse tree produced by SystemVerilogParser#remain_active_flag.
Visit a parse tree produced by SystemVerilogParser#remain_active_flag.
ctx
the parse tree
returns
the visitor result
abstract def visitRemain_active_flag_opt(ctx: Remain_active_flag_optContext): T
Visit a parse tree produced by SystemVerilogParser#remain_active_flag_opt.
Visit a parse tree produced by SystemVerilogParser#remain_active_flag_opt.
ctx
the parse tree
returns
the visitor result
abstract def visitRemoval_timing_check(ctx: Removal_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#removal_timing_check.
Visit a parse tree produced by SystemVerilogParser#removal_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitRepeat_range(ctx: Repeat_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#repeat_range.
Visit a parse tree produced by SystemVerilogParser#repeat_range.
ctx
the parse tree
returns
the visitor result
abstract def visitRestrict_property_statement(ctx: Restrict_property_statementContext): T
Visit a parse tree produced by SystemVerilogParser#restrict_property_statement.
Visit a parse tree produced by SystemVerilogParser#restrict_property_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitRs_case(ctx: Rs_caseContext): T
Visit a parse tree produced by SystemVerilogParser#rs_case.
Visit a parse tree produced by SystemVerilogParser#rs_case.
ctx
the parse tree
returns
the visitor result
abstract def visitRs_case_item(ctx: Rs_case_itemContext): T
Visit a parse tree produced by SystemVerilogParser#rs_case_item.
Visit a parse tree produced by SystemVerilogParser#rs_case_item.
ctx
the parse tree
returns
the visitor result
abstract def visitRs_code_block(ctx: Rs_code_blockContext): T
Visit a parse tree produced by SystemVerilogParser#rs_code_block.
Visit a parse tree produced by SystemVerilogParser#rs_code_block.
ctx
the parse tree
returns
the visitor result
abstract def visitRs_if_else(ctx: Rs_if_elseContext): T
Visit a parse tree produced by SystemVerilogParser#rs_if_else.
Visit a parse tree produced by SystemVerilogParser#rs_if_else.
ctx
the parse tree
returns
the visitor result
abstract def visitRs_prod(ctx: Rs_prodContext): T
Visit a parse tree produced by SystemVerilogParser#rs_prod.
Visit a parse tree produced by SystemVerilogParser#rs_prod.
ctx
the parse tree
returns
the visitor result
abstract def visitRs_production_list(ctx: Rs_production_listContext): T
Visit a parse tree produced by SystemVerilogParser#rs_production_list.
Visit a parse tree produced by SystemVerilogParser#rs_production_list.
ctx
the parse tree
returns
the visitor result
abstract def visitRs_repeat(ctx: Rs_repeatContext): T
Visit a parse tree produced by SystemVerilogParser#rs_repeat.
Visit a parse tree produced by SystemVerilogParser#rs_repeat.
ctx
the parse tree
returns
the visitor result
abstract def visitRs_rule(ctx: Rs_ruleContext): T
Visit a parse tree produced by SystemVerilogParser#rs_rule.
Visit a parse tree produced by SystemVerilogParser#rs_rule.
ctx
the parse tree
returns
the visitor result
abstract def visitScalar_constant(ctx: Scalar_constantContext): T
Visit a parse tree produced by SystemVerilogParser#scalar_constant.
Visit a parse tree produced by SystemVerilogParser#scalar_constant.
ctx
the parse tree
returns
the visitor result
abstract def visitScalar_timing_check_condition(ctx: Scalar_timing_check_conditionContext): T
Visit a parse tree produced by SystemVerilogParser#scalar_timing_check_condition.
Visit a parse tree produced by SystemVerilogParser#scalar_timing_check_condition.
ctx
the parse tree
returns
the visitor result
abstract def visitSelect_(ctx: Select_Context): T
Visit a parse tree produced by SystemVerilogParser#select_.
Visit a parse tree produced by SystemVerilogParser#select_.
ctx
the parse tree
returns
the visitor result
abstract def visitSelect_condition(ctx: Select_conditionContext): T
Visit a parse tree produced by SystemVerilogParser#select_condition.
Visit a parse tree produced by SystemVerilogParser#select_condition.
ctx
the parse tree
returns
the visitor result
abstract def visitSelect_expression(ctx: Select_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#select_expression.
Visit a parse tree produced by SystemVerilogParser#select_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitSeq_arg_list(ctx: Seq_arg_listContext): T
Visit a parse tree produced by SystemVerilogParser#seq_arg_list.
Visit a parse tree produced by SystemVerilogParser#seq_arg_list.
ctx
the parse tree
returns
the visitor result
abstract def visitSeq_block(ctx: Seq_blockContext): T
Visit a parse tree produced by SystemVerilogParser#seq_block.
Visit a parse tree produced by SystemVerilogParser#seq_block.
ctx
the parse tree
returns
the visitor result
abstract def visitSeq_input_list(ctx: Seq_input_listContext): T
Visit a parse tree produced by SystemVerilogParser#seq_input_list.
Visit a parse tree produced by SystemVerilogParser#seq_input_list.
ctx
the parse tree
returns
the visitor result
abstract def visitSeq_named_arg(ctx: Seq_named_argContext): T
Visit a parse tree produced by SystemVerilogParser#seq_named_arg.
Visit a parse tree produced by SystemVerilogParser#seq_named_arg.
ctx
the parse tree
returns
the visitor result
abstract def visitSeq_ordered_arg(ctx: Seq_ordered_argContext): T
Visit a parse tree produced by SystemVerilogParser#seq_ordered_arg.
Visit a parse tree produced by SystemVerilogParser#seq_ordered_arg.
ctx
the parse tree
returns
the visitor result
abstract def visitSeq_port_item_local(ctx: Seq_port_item_localContext): T
Visit a parse tree produced by SystemVerilogParser#seq_port_item_local.
Visit a parse tree produced by SystemVerilogParser#seq_port_item_local.
ctx
the parse tree
returns
the visitor result
abstract def visitSeq_port_list(ctx: Seq_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#seq_port_list.
Visit a parse tree produced by SystemVerilogParser#seq_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_abbrev(ctx: Sequence_abbrevContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_abbrev.
Visit a parse tree produced by SystemVerilogParser#sequence_abbrev.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_actual_arg(ctx: Sequence_actual_argContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_actual_arg.
Visit a parse tree produced by SystemVerilogParser#sequence_actual_arg.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_declaration(ctx: Sequence_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_declaration.
Visit a parse tree produced by SystemVerilogParser#sequence_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_expr(ctx: Sequence_exprContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_expr.
Visit a parse tree produced by SystemVerilogParser#sequence_expr.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_formal_type(ctx: Sequence_formal_typeContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_formal_type.
Visit a parse tree produced by SystemVerilogParser#sequence_formal_type.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_identifier(ctx: Sequence_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_identifier.
Visit a parse tree produced by SystemVerilogParser#sequence_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_instance(ctx: Sequence_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_instance.
Visit a parse tree produced by SystemVerilogParser#sequence_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_list_of_arguments(ctx: Sequence_list_of_argumentsContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_list_of_arguments.
Visit a parse tree produced by SystemVerilogParser#sequence_list_of_arguments.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_lvar_port_direction(ctx: Sequence_lvar_port_directionContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_lvar_port_direction.
Visit a parse tree produced by SystemVerilogParser#sequence_lvar_port_direction.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_match_item(ctx: Sequence_match_itemContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_match_item.
Visit a parse tree produced by SystemVerilogParser#sequence_match_item.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_method_call(ctx: Sequence_method_callContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_method_call.
Visit a parse tree produced by SystemVerilogParser#sequence_method_call.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_name(ctx: Sequence_nameContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_name.
Visit a parse tree produced by SystemVerilogParser#sequence_name.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_port_item(ctx: Sequence_port_itemContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_port_item.
Visit a parse tree produced by SystemVerilogParser#sequence_port_item.
ctx
the parse tree
returns
the visitor result
abstract def visitSequence_port_list(ctx: Sequence_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#sequence_port_list.
Visit a parse tree produced by SystemVerilogParser#sequence_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitSequential_body(ctx: Sequential_bodyContext): T
Visit a parse tree produced by SystemVerilogParser#sequential_body.
Visit a parse tree produced by SystemVerilogParser#sequential_body.
ctx
the parse tree
returns
the visitor result
abstract def visitSequential_entry(ctx: Sequential_entryContext): T
Visit a parse tree produced by SystemVerilogParser#sequential_entry.
Visit a parse tree produced by SystemVerilogParser#sequential_entry.
ctx
the parse tree
returns
the visitor result
abstract def visitSet_covergroup_expression(ctx: Set_covergroup_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#set_covergroup_expression.
Visit a parse tree produced by SystemVerilogParser#set_covergroup_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitSetup_timing_check(ctx: Setup_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#setup_timing_check.
Visit a parse tree produced by SystemVerilogParser#setup_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitSetuphold_timing_check(ctx: Setuphold_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#setuphold_timing_check.
Visit a parse tree produced by SystemVerilogParser#setuphold_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitShowcancelled_declaration(ctx: Showcancelled_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#showcancelled_declaration.
Visit a parse tree produced by SystemVerilogParser#showcancelled_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitSignal_identifier(ctx: Signal_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#signal_identifier.
Visit a parse tree produced by SystemVerilogParser#signal_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitSigning(ctx: SigningContext): T
Visit a parse tree produced by SystemVerilogParser#signing.
Visit a parse tree produced by SystemVerilogParser#signing.
ctx
the parse tree
returns
the visitor result
abstract def visitSimple_identifier(ctx: Simple_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#simple_identifier.
Visit a parse tree produced by SystemVerilogParser#simple_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitSimple_immediate_assert_statement(ctx: Simple_immediate_assert_statementContext): T
Visit a parse tree produced by SystemVerilogParser#simple_immediate_assert_statement.
Visit a parse tree produced by SystemVerilogParser#simple_immediate_assert_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitSimple_immediate_assertion_statement(ctx: Simple_immediate_assertion_statementContext): T
Visit a parse tree produced by SystemVerilogParser#simple_immediate_assertion_statement.
Visit a parse tree produced by SystemVerilogParser#simple_immediate_assertion_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitSimple_immediate_assume_statement(ctx: Simple_immediate_assume_statementContext): T
Visit a parse tree produced by SystemVerilogParser#simple_immediate_assume_statement.
Visit a parse tree produced by SystemVerilogParser#simple_immediate_assume_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitSimple_immediate_cover_statement(ctx: Simple_immediate_cover_statementContext): T
Visit a parse tree produced by SystemVerilogParser#simple_immediate_cover_statement.
Visit a parse tree produced by SystemVerilogParser#simple_immediate_cover_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitSimple_path_declaration(ctx: Simple_path_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#simple_path_declaration.
Visit a parse tree produced by SystemVerilogParser#simple_path_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitSimple_type(ctx: Simple_typeContext): T
Visit a parse tree produced by SystemVerilogParser#simple_type.
Visit a parse tree produced by SystemVerilogParser#simple_type.
ctx
the parse tree
returns
the visitor result
abstract def visitSize(ctx: SizeContext): T
Visit a parse tree produced by SystemVerilogParser#size.
Visit a parse tree produced by SystemVerilogParser#size.
ctx
the parse tree
returns
the visitor result
abstract def visitSkew_timing_check(ctx: Skew_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#skew_timing_check.
Visit a parse tree produced by SystemVerilogParser#skew_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitSkew_timing_check_opt(ctx: Skew_timing_check_optContext): T
Visit a parse tree produced by SystemVerilogParser#skew_timing_check_opt.
Visit a parse tree produced by SystemVerilogParser#skew_timing_check_opt.
ctx
the parse tree
returns
the visitor result
abstract def visitSlice_size(ctx: Slice_sizeContext): T
Visit a parse tree produced by SystemVerilogParser#slice_size.
Visit a parse tree produced by SystemVerilogParser#slice_size.
ctx
the parse tree
returns
the visitor result
abstract def visitSolve_before_list(ctx: Solve_before_listContext): T
Visit a parse tree produced by SystemVerilogParser#solve_before_list.
Visit a parse tree produced by SystemVerilogParser#solve_before_list.
ctx
the parse tree
returns
the visitor result
abstract def visitSource_text(ctx: Source_textContext): T
Visit a parse tree produced by SystemVerilogParser#source_text.
Visit a parse tree produced by SystemVerilogParser#source_text.
ctx
the parse tree
returns
the visitor result
abstract def visitSpecify_block(ctx: Specify_blockContext): T
Visit a parse tree produced by SystemVerilogParser#specify_block.
Visit a parse tree produced by SystemVerilogParser#specify_block.
ctx
the parse tree
returns
the visitor result
abstract def visitSpecify_input_terminal_descriptor(ctx: Specify_input_terminal_descriptorContext): T
Visit a parse tree produced by SystemVerilogParser#specify_input_terminal_descriptor.
Visit a parse tree produced by SystemVerilogParser#specify_input_terminal_descriptor.
ctx
the parse tree
returns
the visitor result
abstract def visitSpecify_item(ctx: Specify_itemContext): T
Visit a parse tree produced by SystemVerilogParser#specify_item.
Visit a parse tree produced by SystemVerilogParser#specify_item.
ctx
the parse tree
returns
the visitor result
abstract def visitSpecify_output_terminal_descriptor(ctx: Specify_output_terminal_descriptorContext): T
Visit a parse tree produced by SystemVerilogParser#specify_output_terminal_descriptor.
Visit a parse tree produced by SystemVerilogParser#specify_output_terminal_descriptor.
ctx
the parse tree
returns
the visitor result
abstract def visitSpecify_terminal_descriptor(ctx: Specify_terminal_descriptorContext): T
Visit a parse tree produced by SystemVerilogParser#specify_terminal_descriptor.
Visit a parse tree produced by SystemVerilogParser#specify_terminal_descriptor.
ctx
the parse tree
returns
the visitor result
abstract def visitSpecparam_assignment(ctx: Specparam_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#specparam_assignment.
Visit a parse tree produced by SystemVerilogParser#specparam_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitSpecparam_declaration(ctx: Specparam_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#specparam_declaration.
Visit a parse tree produced by SystemVerilogParser#specparam_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitSpecparam_identifier(ctx: Specparam_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#specparam_identifier.
Visit a parse tree produced by SystemVerilogParser#specparam_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitStart_edge_offset(ctx: Start_edge_offsetContext): T
Visit a parse tree produced by SystemVerilogParser#start_edge_offset.
Visit a parse tree produced by SystemVerilogParser#start_edge_offset.
ctx
the parse tree
returns
the visitor result
abstract def visitState_dependent_path_declaration(ctx: State_dependent_path_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#state_dependent_path_declaration.
Visit a parse tree produced by SystemVerilogParser#state_dependent_path_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitStatement(ctx: StatementContext): T
Visit a parse tree produced by SystemVerilogParser#statement.
Visit a parse tree produced by SystemVerilogParser#statement.
ctx
the parse tree
returns
the visitor result
abstract def visitStatement_item(ctx: Statement_itemContext): T
Visit a parse tree produced by SystemVerilogParser#statement_item.
Visit a parse tree produced by SystemVerilogParser#statement_item.
ctx
the parse tree
returns
the visitor result
abstract def visitStatement_or_null(ctx: Statement_or_nullContext): T
Visit a parse tree produced by SystemVerilogParser#statement_or_null.
Visit a parse tree produced by SystemVerilogParser#statement_or_null.
ctx
the parse tree
returns
the visitor result
abstract def visitStream_concatenation(ctx: Stream_concatenationContext): T
Visit a parse tree produced by SystemVerilogParser#stream_concatenation.
Visit a parse tree produced by SystemVerilogParser#stream_concatenation.
ctx
the parse tree
returns
the visitor result
abstract def visitStream_expression(ctx: Stream_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#stream_expression.
Visit a parse tree produced by SystemVerilogParser#stream_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitStream_operator(ctx: Stream_operatorContext): T
Visit a parse tree produced by SystemVerilogParser#stream_operator.
Visit a parse tree produced by SystemVerilogParser#stream_operator.
ctx
the parse tree
returns
the visitor result
abstract def visitStreaming_concatenation(ctx: Streaming_concatenationContext): T
Visit a parse tree produced by SystemVerilogParser#streaming_concatenation.
Visit a parse tree produced by SystemVerilogParser#streaming_concatenation.
ctx
the parse tree
returns
the visitor result
abstract def visitStrength0(ctx: Strength0Context): T
Visit a parse tree produced by SystemVerilogParser#strength0.
Visit a parse tree produced by SystemVerilogParser#strength0.
ctx
the parse tree
returns
the visitor result
abstract def visitStrength1(ctx: Strength1Context): T
Visit a parse tree produced by SystemVerilogParser#strength1.
Visit a parse tree produced by SystemVerilogParser#strength1.
ctx
the parse tree
returns
the visitor result
abstract def visitString_literal(ctx: String_literalContext): T
Visit a parse tree produced by SystemVerilogParser#string_literal.
Visit a parse tree produced by SystemVerilogParser#string_literal.
ctx
the parse tree
returns
the visitor result
abstract def visitStruct_union(ctx: Struct_unionContext): T
Visit a parse tree produced by SystemVerilogParser#struct_union.
Visit a parse tree produced by SystemVerilogParser#struct_union.
ctx
the parse tree
returns
the visitor result
abstract def visitStruct_union_member(ctx: Struct_union_memberContext): T
Visit a parse tree produced by SystemVerilogParser#struct_union_member.
Visit a parse tree produced by SystemVerilogParser#struct_union_member.
ctx
the parse tree
returns
the visitor result
abstract def visitSubroutine_call(ctx: Subroutine_callContext): T
Visit a parse tree produced by SystemVerilogParser#subroutine_call.
Visit a parse tree produced by SystemVerilogParser#subroutine_call.
ctx
the parse tree
returns
the visitor result
abstract def visitSubroutine_call_statement(ctx: Subroutine_call_statementContext): T
Visit a parse tree produced by SystemVerilogParser#subroutine_call_statement.
Visit a parse tree produced by SystemVerilogParser#subroutine_call_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitSuper_class_constructor_call(ctx: Super_class_constructor_callContext): T
Visit a parse tree produced by SystemVerilogParser#super_class_constructor_call.
Visit a parse tree produced by SystemVerilogParser#super_class_constructor_call.
ctx
the parse tree
returns
the visitor result
abstract def visitSystem_tf_call(ctx: System_tf_callContext): T
Visit a parse tree produced by SystemVerilogParser#system_tf_call.
Visit a parse tree produced by SystemVerilogParser#system_tf_call.
ctx
the parse tree
returns
the visitor result
abstract def visitSystem_tf_identifier(ctx: System_tf_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#system_tf_identifier.
Visit a parse tree produced by SystemVerilogParser#system_tf_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitSystem_timing_check(ctx: System_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#system_timing_check.
Visit a parse tree produced by SystemVerilogParser#system_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitT01_path_delay_expression(ctx: T01_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#t01_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#t01_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitT0x_path_delay_expression(ctx: T0x_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#t0x_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#t0x_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitT0z_path_delay_expression(ctx: T0z_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#t0z_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#t0z_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitT10_path_delay_expression(ctx: T10_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#t10_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#t10_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitT1x_path_delay_expression(ctx: T1x_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#t1x_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#t1x_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitT1z_path_delay_expression(ctx: T1z_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#t1z_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#t1z_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitT_path_delay_expression(ctx: T_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#t_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#t_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitTagged_union_expression(ctx: Tagged_union_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#tagged_union_expression.
Visit a parse tree produced by SystemVerilogParser#tagged_union_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitTask_body_declaration(ctx: Task_body_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#task_body_declaration.
Visit a parse tree produced by SystemVerilogParser#task_body_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitTask_declaration(ctx: Task_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#task_declaration.
Visit a parse tree produced by SystemVerilogParser#task_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitTask_identifier(ctx: Task_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#task_identifier.
Visit a parse tree produced by SystemVerilogParser#task_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitTask_name(ctx: Task_nameContext): T
Visit a parse tree produced by SystemVerilogParser#task_name.
Visit a parse tree produced by SystemVerilogParser#task_name.
ctx
the parse tree
returns
the visitor result
abstract def visitTask_prototype(ctx: Task_prototypeContext): T
Visit a parse tree produced by SystemVerilogParser#task_prototype.
Visit a parse tree produced by SystemVerilogParser#task_prototype.
ctx
the parse tree
returns
the visitor result
abstract def visitTerminal(arg0: TerminalNode): T
Definition Classes
ParseTreeVisitor
abstract def visitTerminal_identifier(ctx: Terminal_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#terminal_identifier.
Visit a parse tree produced by SystemVerilogParser#terminal_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitTf_identifier(ctx: Tf_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#tf_identifier.
Visit a parse tree produced by SystemVerilogParser#tf_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitTf_item_declaration(ctx: Tf_item_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#tf_item_declaration.
Visit a parse tree produced by SystemVerilogParser#tf_item_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitTf_port_declaration(ctx: Tf_port_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#tf_port_declaration.
Visit a parse tree produced by SystemVerilogParser#tf_port_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitTf_port_direction(ctx: Tf_port_directionContext): T
Visit a parse tree produced by SystemVerilogParser#tf_port_direction.
Visit a parse tree produced by SystemVerilogParser#tf_port_direction.
ctx
the parse tree
returns
the visitor result
abstract def visitTf_port_id(ctx: Tf_port_idContext): T
Visit a parse tree produced by SystemVerilogParser#tf_port_id.
Visit a parse tree produced by SystemVerilogParser#tf_port_id.
ctx
the parse tree
returns
the visitor result
abstract def visitTf_port_item(ctx: Tf_port_itemContext): T
Visit a parse tree produced by SystemVerilogParser#tf_port_item.
Visit a parse tree produced by SystemVerilogParser#tf_port_item.
ctx
the parse tree
returns
the visitor result
abstract def visitTf_port_list(ctx: Tf_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#tf_port_list.
Visit a parse tree produced by SystemVerilogParser#tf_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitTf_var_id(ctx: Tf_var_idContext): T
Visit a parse tree produced by SystemVerilogParser#tf_var_id.
Visit a parse tree produced by SystemVerilogParser#tf_var_id.
ctx
the parse tree
returns
the visitor result
abstract def visitTfall_path_delay_expression(ctx: Tfall_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#tfall_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#tfall_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitThreshold(ctx: ThresholdContext): T
Visit a parse tree produced by SystemVerilogParser#threshold.
Visit a parse tree produced by SystemVerilogParser#threshold.
ctx
the parse tree
returns
the visitor result
abstract def visitTime_literal(ctx: Time_literalContext): T
Visit a parse tree produced by SystemVerilogParser#time_literal.
Visit a parse tree produced by SystemVerilogParser#time_literal.
ctx
the parse tree
returns
the visitor result
abstract def visitTimecheck_cond_opt(ctx: Timecheck_cond_optContext): T
Visit a parse tree produced by SystemVerilogParser#timecheck_cond_opt.
Visit a parse tree produced by SystemVerilogParser#timecheck_cond_opt.
ctx
the parse tree
returns
the visitor result
abstract def visitTimecheck_condition(ctx: Timecheck_conditionContext): T
Visit a parse tree produced by SystemVerilogParser#timecheck_condition.
Visit a parse tree produced by SystemVerilogParser#timecheck_condition.
ctx
the parse tree
returns
the visitor result
abstract def visitTimeskew_timing_check(ctx: Timeskew_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#timeskew_timing_check.
Visit a parse tree produced by SystemVerilogParser#timeskew_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitTimestamp_cond_opt(ctx: Timestamp_cond_optContext): T
Visit a parse tree produced by SystemVerilogParser#timestamp_cond_opt.
Visit a parse tree produced by SystemVerilogParser#timestamp_cond_opt.
ctx
the parse tree
returns
the visitor result
abstract def visitTimestamp_condition(ctx: Timestamp_conditionContext): T
Visit a parse tree produced by SystemVerilogParser#timestamp_condition.
Visit a parse tree produced by SystemVerilogParser#timestamp_condition.
ctx
the parse tree
returns
the visitor result
abstract def visitTimeunits_declaration(ctx: Timeunits_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#timeunits_declaration.
Visit a parse tree produced by SystemVerilogParser#timeunits_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitTiming_check_condition(ctx: Timing_check_conditionContext): T
Visit a parse tree produced by SystemVerilogParser#timing_check_condition.
Visit a parse tree produced by SystemVerilogParser#timing_check_condition.
ctx
the parse tree
returns
the visitor result
abstract def visitTiming_check_event(ctx: Timing_check_eventContext): T
Visit a parse tree produced by SystemVerilogParser#timing_check_event.
Visit a parse tree produced by SystemVerilogParser#timing_check_event.
ctx
the parse tree
returns
the visitor result
abstract def visitTiming_check_event_control(ctx: Timing_check_event_controlContext): T
Visit a parse tree produced by SystemVerilogParser#timing_check_event_control.
Visit a parse tree produced by SystemVerilogParser#timing_check_event_control.
ctx
the parse tree
returns
the visitor result
abstract def visitTiming_check_limit(ctx: Timing_check_limitContext): T
Visit a parse tree produced by SystemVerilogParser#timing_check_limit.
Visit a parse tree produced by SystemVerilogParser#timing_check_limit.
ctx
the parse tree
returns
the visitor result
abstract def visitTiming_check_opt(ctx: Timing_check_optContext): T
Visit a parse tree produced by SystemVerilogParser#timing_check_opt.
Visit a parse tree produced by SystemVerilogParser#timing_check_opt.
ctx
the parse tree
returns
the visitor result
abstract def visitTopmodule_identifier(ctx: Topmodule_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#topmodule_identifier.
Visit a parse tree produced by SystemVerilogParser#topmodule_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitTrans_item(ctx: Trans_itemContext): T
Visit a parse tree produced by SystemVerilogParser#trans_item.
Visit a parse tree produced by SystemVerilogParser#trans_item.
ctx
the parse tree
returns
the visitor result
abstract def visitTrans_list(ctx: Trans_listContext): T
Visit a parse tree produced by SystemVerilogParser#trans_list.
Visit a parse tree produced by SystemVerilogParser#trans_list.
ctx
the parse tree
returns
the visitor result
abstract def visitTrans_range_list(ctx: Trans_range_listContext): T
Visit a parse tree produced by SystemVerilogParser#trans_range_list.
Visit a parse tree produced by SystemVerilogParser#trans_range_list.
ctx
the parse tree
returns
the visitor result
abstract def visitTrans_set(ctx: Trans_setContext): T
Visit a parse tree produced by SystemVerilogParser#trans_set.
Visit a parse tree produced by SystemVerilogParser#trans_set.
ctx
the parse tree
returns
the visitor result
abstract def visitTrise_path_delay_expression(ctx: Trise_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#trise_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#trise_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitTx0_path_delay_expression(ctx: Tx0_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#tx0_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#tx0_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitTx1_path_delay_expression(ctx: Tx1_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#tx1_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#tx1_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitTxz_path_delay_expression(ctx: Txz_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#txz_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#txz_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitType_assignment(ctx: Type_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#type_assignment.
Visit a parse tree produced by SystemVerilogParser#type_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitType_declaration(ctx: Type_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#type_declaration.
Visit a parse tree produced by SystemVerilogParser#type_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitType_identifier(ctx: Type_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#type_identifier.
Visit a parse tree produced by SystemVerilogParser#type_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitType_reference(ctx: Type_referenceContext): T
Visit a parse tree produced by SystemVerilogParser#type_reference.
Visit a parse tree produced by SystemVerilogParser#type_reference.
ctx
the parse tree
returns
the visitor result
abstract def visitTz0_path_delay_expression(ctx: Tz0_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#tz0_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#tz0_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitTz1_path_delay_expression(ctx: Tz1_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#tz1_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#tz1_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitTz_path_delay_expression(ctx: Tz_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#tz_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#tz_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitTzx_path_delay_expression(ctx: Tzx_path_delay_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#tzx_path_delay_expression.
Visit a parse tree produced by SystemVerilogParser#tzx_path_delay_expression.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_ansi_declaration(ctx: Udp_ansi_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#udp_ansi_declaration.
Visit a parse tree produced by SystemVerilogParser#udp_ansi_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_body(ctx: Udp_bodyContext): T
Visit a parse tree produced by SystemVerilogParser#udp_body.
Visit a parse tree produced by SystemVerilogParser#udp_body.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_declaration(ctx: Udp_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#udp_declaration.
Visit a parse tree produced by SystemVerilogParser#udp_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_declaration_port_list(ctx: Udp_declaration_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#udp_declaration_port_list.
Visit a parse tree produced by SystemVerilogParser#udp_declaration_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_identifier(ctx: Udp_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#udp_identifier.
Visit a parse tree produced by SystemVerilogParser#udp_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_initial_statement(ctx: Udp_initial_statementContext): T
Visit a parse tree produced by SystemVerilogParser#udp_initial_statement.
Visit a parse tree produced by SystemVerilogParser#udp_initial_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_input_declaration(ctx: Udp_input_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#udp_input_declaration.
Visit a parse tree produced by SystemVerilogParser#udp_input_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_instance(ctx: Udp_instanceContext): T
Visit a parse tree produced by SystemVerilogParser#udp_instance.
Visit a parse tree produced by SystemVerilogParser#udp_instance.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_instantiation(ctx: Udp_instantiationContext): T
Visit a parse tree produced by SystemVerilogParser#udp_instantiation.
Visit a parse tree produced by SystemVerilogParser#udp_instantiation.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_name(ctx: Udp_nameContext): T
Visit a parse tree produced by SystemVerilogParser#udp_name.
Visit a parse tree produced by SystemVerilogParser#udp_name.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_nonansi_declaration(ctx: Udp_nonansi_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#udp_nonansi_declaration.
Visit a parse tree produced by SystemVerilogParser#udp_nonansi_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_output_declaration(ctx: Udp_output_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#udp_output_declaration.
Visit a parse tree produced by SystemVerilogParser#udp_output_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_port_declaration(ctx: Udp_port_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#udp_port_declaration.
Visit a parse tree produced by SystemVerilogParser#udp_port_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_port_list(ctx: Udp_port_listContext): T
Visit a parse tree produced by SystemVerilogParser#udp_port_list.
Visit a parse tree produced by SystemVerilogParser#udp_port_list.
ctx
the parse tree
returns
the visitor result
abstract def visitUdp_reg_declaration(ctx: Udp_reg_declarationContext): T
Visit a parse tree produced by SystemVerilogParser#udp_reg_declaration.
Visit a parse tree produced by SystemVerilogParser#udp_reg_declaration.
ctx
the parse tree
returns
the visitor result
abstract def visitUnary_module_path_operator(ctx: Unary_module_path_operatorContext): T
Visit a parse tree produced by SystemVerilogParser#unary_module_path_operator.
Visit a parse tree produced by SystemVerilogParser#unary_module_path_operator.
ctx
the parse tree
returns
the visitor result
abstract def visitUnary_operator(ctx: Unary_operatorContext): T
Visit a parse tree produced by SystemVerilogParser#unary_operator.
Visit a parse tree produced by SystemVerilogParser#unary_operator.
ctx
the parse tree
returns
the visitor result
abstract def visitUnbased_unsized_literal(ctx: Unbased_unsized_literalContext): T
Visit a parse tree produced by SystemVerilogParser#unbased_unsized_literal.
Visit a parse tree produced by SystemVerilogParser#unbased_unsized_literal.
ctx
the parse tree
returns
the visitor result
abstract def visitUnique_priority(ctx: Unique_priorityContext): T
Visit a parse tree produced by SystemVerilogParser#unique_priority.
Visit a parse tree produced by SystemVerilogParser#unique_priority.
ctx
the parse tree
returns
the visitor result
abstract def visitUniqueness_constraint(ctx: Uniqueness_constraintContext): T
Visit a parse tree produced by SystemVerilogParser#uniqueness_constraint.
Visit a parse tree produced by SystemVerilogParser#uniqueness_constraint.
ctx
the parse tree
returns
the visitor result
abstract def visitUnpacked_dimension(ctx: Unpacked_dimensionContext): T
Visit a parse tree produced by SystemVerilogParser#unpacked_dimension.
Visit a parse tree produced by SystemVerilogParser#unpacked_dimension.
ctx
the parse tree
returns
the visitor result
abstract def visitUnsigned_number(ctx: Unsigned_numberContext): T
Visit a parse tree produced by SystemVerilogParser#unsigned_number.
Visit a parse tree produced by SystemVerilogParser#unsigned_number.
ctx
the parse tree
returns
the visitor result
abstract def visitUnsized_dimension(ctx: Unsized_dimensionContext): T
Visit a parse tree produced by SystemVerilogParser#unsized_dimension.
Visit a parse tree produced by SystemVerilogParser#unsized_dimension.
ctx
the parse tree
returns
the visitor result
abstract def visitUse_clause(ctx: Use_clauseContext): T
Visit a parse tree produced by SystemVerilogParser#use_clause.
Visit a parse tree produced by SystemVerilogParser#use_clause.
ctx
the parse tree
returns
the visitor result
abstract def visitValue_range(ctx: Value_rangeContext): T
Visit a parse tree produced by SystemVerilogParser#value_range.
Visit a parse tree produced by SystemVerilogParser#value_range.
ctx
the parse tree
returns
the visitor result
abstract def visitVar_data_type(ctx: Var_data_typeContext): T
Visit a parse tree produced by SystemVerilogParser#var_data_type.
Visit a parse tree produced by SystemVerilogParser#var_data_type.
ctx
the parse tree
returns
the visitor result
abstract def visitVar_id(ctx: Var_idContext): T
Visit a parse tree produced by SystemVerilogParser#var_id.
Visit a parse tree produced by SystemVerilogParser#var_id.
ctx
the parse tree
returns
the visitor result
abstract def visitVar_port_id(ctx: Var_port_idContext): T
Visit a parse tree produced by SystemVerilogParser#var_port_id.
Visit a parse tree produced by SystemVerilogParser#var_port_id.
ctx
the parse tree
returns
the visitor result
abstract def visitVariable_assignment(ctx: Variable_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#variable_assignment.
Visit a parse tree produced by SystemVerilogParser#variable_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitVariable_decl_assignment(ctx: Variable_decl_assignmentContext): T
Visit a parse tree produced by SystemVerilogParser#variable_decl_assignment.
Visit a parse tree produced by SystemVerilogParser#variable_decl_assignment.
ctx
the parse tree
returns
the visitor result
abstract def visitVariable_dimension(ctx: Variable_dimensionContext): T
Visit a parse tree produced by SystemVerilogParser#variable_dimension.
Visit a parse tree produced by SystemVerilogParser#variable_dimension.
ctx
the parse tree
returns
the visitor result
abstract def visitVariable_identifier(ctx: Variable_identifierContext): T
Visit a parse tree produced by SystemVerilogParser#variable_identifier.
Visit a parse tree produced by SystemVerilogParser#variable_identifier.
ctx
the parse tree
returns
the visitor result
abstract def visitVariable_identifier_list(ctx: Variable_identifier_listContext): T
Visit a parse tree produced by SystemVerilogParser#variable_identifier_list.
Visit a parse tree produced by SystemVerilogParser#variable_identifier_list.
ctx
the parse tree
returns
the visitor result
abstract def visitVariable_lvalue(ctx: Variable_lvalueContext): T
Visit a parse tree produced by SystemVerilogParser#variable_lvalue.
Visit a parse tree produced by SystemVerilogParser#variable_lvalue.
ctx
the parse tree
returns
the visitor result
abstract def visitVariable_port_type(ctx: Variable_port_typeContext): T
Visit a parse tree produced by SystemVerilogParser#variable_port_type.
Visit a parse tree produced by SystemVerilogParser#variable_port_type.
ctx
the parse tree
returns
the visitor result
abstract def visitWait_statement(ctx: Wait_statementContext): T
Visit a parse tree produced by SystemVerilogParser#wait_statement.
Visit a parse tree produced by SystemVerilogParser#wait_statement.
ctx
the parse tree
returns
the visitor result
abstract def visitWeight_spec(ctx: Weight_specContext): T
Visit a parse tree produced by SystemVerilogParser#weight_spec.
Visit a parse tree produced by SystemVerilogParser#weight_spec.
ctx
the parse tree
returns
the visitor result
abstract def visitWeight_specification(ctx: Weight_specificationContext): T
Visit a parse tree produced by SystemVerilogParser#weight_specification.
Visit a parse tree produced by SystemVerilogParser#weight_specification.
ctx
the parse tree
returns
the visitor result
abstract def visitWidth_timing_check(ctx: Width_timing_checkContext): T
Visit a parse tree produced by SystemVerilogParser#width_timing_check.
Visit a parse tree produced by SystemVerilogParser#width_timing_check.
ctx
the parse tree
returns
the visitor result
abstract def visitWith_covergroup_expression(ctx: With_covergroup_expressionContext): T
Visit a parse tree produced by SystemVerilogParser#with_covergroup_expression.
Visit a parse tree produced by SystemVerilogParser#with_covergroup_expression.
ctx
the parse tree
returns
the visitor result

Concrete Value Members

final def !=(arg0: Any): Boolean
Definition Classes
AnyRef → Any
final def ##: Int
Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean
Definition Classes
AnyRef → Any
final def asInstanceOf[T0]: T0
Definition Classes
Any
def clone(): AnyRef
Attributes
protected[lang]
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.CloneNotSupportedException]) @IntrinsicCandidate() @native()
final def eq(arg0: AnyRef): Boolean
Definition Classes
AnyRef
def equals(arg0: AnyRef): Boolean
Definition Classes
AnyRef → Any
final def getClass(): Class[_ <: AnyRef]
Definition Classes
AnyRef → Any
Annotations
@IntrinsicCandidate() @native()
def hashCode(): Int
Definition Classes
AnyRef → Any
Annotations
@IntrinsicCandidate() @native()
final def isInstanceOf[T0]: Boolean
Definition Classes
Any
final def ne(arg0: AnyRef): Boolean
Definition Classes
AnyRef
final def notify(): Unit
Definition Classes
AnyRef
Annotations
@IntrinsicCandidate() @native()
final def notifyAll(): Unit
Definition Classes
AnyRef
Annotations
@IntrinsicCandidate() @native()
final def synchronized[T0](arg0: => T0): T0
Definition Classes
AnyRef
def toString(): String
Definition Classes
AnyRef → Any
final def wait(arg0: Long, arg1: Int): Unit
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.InterruptedException])
final def wait(arg0: Long): Unit
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.InterruptedException]) @native()
final def wait(): Unit
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.InterruptedException])

Deprecated Value Members

def finalize(): Unit
Attributes
protected[lang]
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.Throwable]) @Deprecated
Deprecated
(Since version 9)

Packages

SystemVerilogParserVisitor

trait SystemVerilogParserVisitor[T] extends ParseTreeVisitor[T]

Abstract Value Members

Concrete Value Members

Deprecated Value Members

Inherited from ParseTreeVisitor[T]

Inherited from AnyRef

Inherited from Any

Ungrouped

Packages

SystemVerilogParserVisitor

trait SystemVerilogParserVisitor[T] extends ParseTreeVisitor[T]

Abstract Value Members

Concrete Value Members

Deprecated Value Members

Inherited from ParseTreeVisitor[T]

Inherited from AnyRef

Inherited from Any

Ungrouped

SystemVerilogParserVisitor