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object ModuleUtils

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  14. def parseSourceSetTopModules(sources: Set[String])(implicit project: ScaledaProject): Set[String]

    Get maybe top module from source sets, will parse all source code

    Get maybe top module from source sets, will parse all source code

    sources

    source set

    returns

    optional top module

  15. def parseVerilogASTModules(tree: Source_textContext): Map[String, Seq[String]]

    Parse a Verilog file and return module names and instances in each module

    Parse a Verilog file and return module names and instances in each module

    tree

    AST

    returns

    modules info

  16. def parseVerilogCodeAST(code: String): Source_textContext

    Parse a Verilog code (text) and return AST

    Parse a Verilog code (text) and return AST

    code

    source code text

    returns

    AST

  17. def parseVerilogCodeModules(code: String): Map[String, Seq[String]]

    Parse a Verilog file and return module names and instances in each module

    Parse a Verilog file and return module names and instances in each module

    code

    Source Code

    returns

    modules info

  18. def parseVerilogFileAST(file: File): Source_textContext

    Parse a Verilog file and return AST

    Parse a Verilog file and return AST

    file

    verilog file

    returns

    AST

  19. def parseVerilogFileModules(file: File): Map[String, Seq[String]]

    Parse a Verilog file and return module names and instances in each module

    Parse a Verilog file and return module names and instances in each module

    file

    Source code file

    returns

    modules info

  20. final def synchronized[T0](arg0: => T0): T0
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  1. def finalize(): Unit
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    Deprecated

    (Since version 9)

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