VerilogParserBaseVisitor

class VerilogParserBaseVisitor[T] extends AbstractParseTreeVisitor[T] with VerilogParserVisitor[T]

This class provides an empty implementation of VerilogParserVisitor, which can be extended to create a visitor which only needs to handle a subset of the available methods.

Annotations: @SuppressWarnings()

Linear Supertypes

VerilogParserVisitor[T], AbstractParseTreeVisitor[T], ParseTreeVisitor[T], AnyRef, Any

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Inherited

VerilogParserBaseVisitor
VerilogParserVisitor
AbstractParseTreeVisitor
ParseTreeVisitor
AnyRef
Any

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Protected

Instance Constructors

new VerilogParserBaseVisitor()

Value Members

final def !=(arg0: Any): Boolean
Definition Classes
AnyRef → Any
final def ##: Int
Definition Classes
AnyRef → Any
final def ==(arg0: Any): Boolean
Definition Classes
AnyRef → Any
def aggregateResult(arg0: T, arg1: T): T
Attributes
protected[tree]
Definition Classes
AbstractParseTreeVisitor
final def asInstanceOf[T0]: T0
Definition Classes
Any
def clone(): AnyRef
Attributes
protected[lang]
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.CloneNotSupportedException]) @IntrinsicCandidate() @native()
def defaultResult(): T
Attributes
protected[tree]
Definition Classes
AbstractParseTreeVisitor
final def eq(arg0: AnyRef): Boolean
Definition Classes
AnyRef
def equals(arg0: AnyRef): Boolean
Definition Classes
AnyRef → Any
final def getClass(): Class[_ <: AnyRef]
Definition Classes
AnyRef → Any
Annotations
@IntrinsicCandidate() @native()
def hashCode(): Int
Definition Classes
AnyRef → Any
Annotations
@IntrinsicCandidate() @native()
final def isInstanceOf[T0]: Boolean
Definition Classes
Any
final def ne(arg0: AnyRef): Boolean
Definition Classes
AnyRef
final def notify(): Unit
Definition Classes
AnyRef
Annotations
@IntrinsicCandidate() @native()
final def notifyAll(): Unit
Definition Classes
AnyRef
Annotations
@IntrinsicCandidate() @native()
def shouldVisitNextChild(arg0: RuleNode, arg1: T): Boolean
Attributes
protected[tree]
Definition Classes
AbstractParseTreeVisitor
final def synchronized[T0](arg0: => T0): T0
Definition Classes
AnyRef
def toString(): String
Definition Classes
AnyRef → Any
def visit(arg0: ParseTree): T
Definition Classes
AbstractParseTreeVisitor → ParseTreeVisitor
def visitAlways_construct(ctx: Always_constructContext): T
Visit a parse tree produced by VerilogParser#always_construct.
Visit a parse tree produced by VerilogParser#always_construct.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitArrayed_identifier(ctx: Arrayed_identifierContext): T
Visit a parse tree produced by VerilogParser#arrayed_identifier.
Visit a parse tree produced by VerilogParser#arrayed_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitAttr_name(ctx: Attr_nameContext): T
Visit a parse tree produced by VerilogParser#attr_name.
Visit a parse tree produced by VerilogParser#attr_name.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitAttr_spec(ctx: Attr_specContext): T
Visit a parse tree produced by VerilogParser#attr_spec.
Visit a parse tree produced by VerilogParser#attr_spec.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitAttribute_instance(ctx: Attribute_instanceContext): T
Visit a parse tree produced by VerilogParser#attribute_instance.
Visit a parse tree produced by VerilogParser#attribute_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitBase_expression(ctx: Base_expressionContext): T
Visit a parse tree produced by VerilogParser#base_expression.
Visit a parse tree produced by VerilogParser#base_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitBinary_module_path_operator(ctx: Binary_module_path_operatorContext): T
Visit a parse tree produced by VerilogParser#binary_module_path_operator.
Visit a parse tree produced by VerilogParser#binary_module_path_operator.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitBinary_operator(ctx: Binary_operatorContext): T
Visit a parse tree produced by VerilogParser#binary_operator.
Visit a parse tree produced by VerilogParser#binary_operator.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitBinary_operator_or(ctx: Binary_operator_orContext): T
Visit a parse tree produced by VerilogParser#binary_operator_or.
Visit a parse tree produced by VerilogParser#binary_operator_or.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitBlock_identifier(ctx: Block_identifierContext): T
Visit a parse tree produced by VerilogParser#block_identifier.
Visit a parse tree produced by VerilogParser#block_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitBlock_item_declaration(ctx: Block_item_declarationContext): T
Visit a parse tree produced by VerilogParser#block_item_declaration.
Visit a parse tree produced by VerilogParser#block_item_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitBlock_reg_declaration(ctx: Block_reg_declarationContext): T
Visit a parse tree produced by VerilogParser#block_reg_declaration.
Visit a parse tree produced by VerilogParser#block_reg_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitBlock_variable_type(ctx: Block_variable_typeContext): T
Visit a parse tree produced by VerilogParser#block_variable_type.
Visit a parse tree produced by VerilogParser#block_variable_type.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitBlocking_assignment(ctx: Blocking_assignmentContext): T
Visit a parse tree produced by VerilogParser#blocking_assignment.
Visit a parse tree produced by VerilogParser#blocking_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCase_body(ctx: Case_bodyContext): T
Visit a parse tree produced by VerilogParser#case_body.
Visit a parse tree produced by VerilogParser#case_body.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCase_default_item(ctx: Case_default_itemContext): T
Visit a parse tree produced by VerilogParser#case_default_item.
Visit a parse tree produced by VerilogParser#case_default_item.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCase_item(ctx: Case_itemContext): T
Visit a parse tree produced by VerilogParser#case_item.
Visit a parse tree produced by VerilogParser#case_item.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCase_statement(ctx: Case_statementContext): T
Visit a parse tree produced by VerilogParser#case_statement.
Visit a parse tree produced by VerilogParser#case_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCell_clause(ctx: Cell_clauseContext): T
Visit a parse tree produced by VerilogParser#cell_clause.
Visit a parse tree produced by VerilogParser#cell_clause.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCell_identifier(ctx: Cell_identifierContext): T
Visit a parse tree produced by VerilogParser#cell_identifier.
Visit a parse tree produced by VerilogParser#cell_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCharge_strength(ctx: Charge_strengthContext): T
Visit a parse tree produced by VerilogParser#charge_strength.
Visit a parse tree produced by VerilogParser#charge_strength.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitChecktime_condition(ctx: Checktime_conditionContext): T
Visit a parse tree produced by VerilogParser#checktime_condition.
Visit a parse tree produced by VerilogParser#checktime_condition.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitChildren(arg0: RuleNode): T
Definition Classes
AbstractParseTreeVisitor → ParseTreeVisitor
def visitCmos_switch_instance(ctx: Cmos_switch_instanceContext): T
Visit a parse tree produced by VerilogParser#cmos_switch_instance.
Visit a parse tree produced by VerilogParser#cmos_switch_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCmos_switchtype(ctx: Cmos_switchtypeContext): T
Visit a parse tree produced by VerilogParser#cmos_switchtype.
Visit a parse tree produced by VerilogParser#cmos_switchtype.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConcatenation(ctx: ConcatenationContext): T
Visit a parse tree produced by VerilogParser#concatenation.
Visit a parse tree produced by VerilogParser#concatenation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConditional_statement(ctx: Conditional_statementContext): T
Visit a parse tree produced by VerilogParser#conditional_statement.
Visit a parse tree produced by VerilogParser#conditional_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConditional_statement_body(ctx: Conditional_statement_bodyContext): T
Visit a parse tree produced by VerilogParser#conditional_statement_body.
Visit a parse tree produced by VerilogParser#conditional_statement_body.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConditional_statement_chain(ctx: Conditional_statement_chainContext): T
Visit a parse tree produced by VerilogParser#conditional_statement_chain.
Visit a parse tree produced by VerilogParser#conditional_statement_chain.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConditional_statement_else_chain(ctx: Conditional_statement_else_chainContext): T
Visit a parse tree produced by VerilogParser#conditional_statement_else_chain.
Visit a parse tree produced by VerilogParser#conditional_statement_else_chain.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConditional_statement_else_tail(ctx: Conditional_statement_else_tailContext): T
Visit a parse tree produced by VerilogParser#conditional_statement_else_tail.
Visit a parse tree produced by VerilogParser#conditional_statement_else_tail.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConditional_statement_head(ctx: Conditional_statement_headContext): T
Visit a parse tree produced by VerilogParser#conditional_statement_head.
Visit a parse tree produced by VerilogParser#conditional_statement_head.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConfig_declaration(ctx: Config_declarationContext): T
Visit a parse tree produced by VerilogParser#config_declaration.
Visit a parse tree produced by VerilogParser#config_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConfig_identifier(ctx: Config_identifierContext): T
Visit a parse tree produced by VerilogParser#config_identifier.
Visit a parse tree produced by VerilogParser#config_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConfig_rule_statement(ctx: Config_rule_statementContext): T
Visit a parse tree produced by VerilogParser#config_rule_statement.
Visit a parse tree produced by VerilogParser#config_rule_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConstant_base_expression(ctx: Constant_base_expressionContext): T
Visit a parse tree produced by VerilogParser#constant_base_expression.
Visit a parse tree produced by VerilogParser#constant_base_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConstant_concatenation(ctx: Constant_concatenationContext): T
Visit a parse tree produced by VerilogParser#constant_concatenation.
Visit a parse tree produced by VerilogParser#constant_concatenation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConstant_expression(ctx: Constant_expressionContext): T
Visit a parse tree produced by VerilogParser#constant_expression.
Visit a parse tree produced by VerilogParser#constant_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConstant_function_call(ctx: Constant_function_callContext): T
Visit a parse tree produced by VerilogParser#constant_function_call.
Visit a parse tree produced by VerilogParser#constant_function_call.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConstant_mintypmax_expression(ctx: Constant_mintypmax_expressionContext): T
Visit a parse tree produced by VerilogParser#constant_mintypmax_expression.
Visit a parse tree produced by VerilogParser#constant_mintypmax_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConstant_multiple_concatenation(ctx: Constant_multiple_concatenationContext): T
Visit a parse tree produced by VerilogParser#constant_multiple_concatenation.
Visit a parse tree produced by VerilogParser#constant_multiple_concatenation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConstant_primary(ctx: Constant_primaryContext): T
Visit a parse tree produced by VerilogParser#constant_primary.
Visit a parse tree produced by VerilogParser#constant_primary.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitConstant_range_expression(ctx: Constant_range_expressionContext): T
Visit a parse tree produced by VerilogParser#constant_range_expression.
Visit a parse tree produced by VerilogParser#constant_range_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitContinuous_assign(ctx: Continuous_assignContext): T
Visit a parse tree produced by VerilogParser#continuous_assign.
Visit a parse tree produced by VerilogParser#continuous_assign.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCreate_defined_flag(ctx: Create_defined_flagContext): T
Visit a parse tree produced by VerilogParser#create_defined_flag.
Visit a parse tree produced by VerilogParser#create_defined_flag.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitCreate_defined_term(ctx: Create_defined_termContext): T
Visit a parse tree produced by VerilogParser#create_defined_term.
Visit a parse tree produced by VerilogParser#create_defined_term.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitData_source_expression(ctx: Data_source_expressionContext): T
Visit a parse tree produced by VerilogParser#data_source_expression.
Visit a parse tree produced by VerilogParser#data_source_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDefault_clause(ctx: Default_clauseContext): T
Visit a parse tree produced by VerilogParser#default_clause.
Visit a parse tree produced by VerilogParser#default_clause.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDefault_nettype_directive(ctx: Default_nettype_directiveContext): T
Visit a parse tree produced by VerilogParser#default_nettype_directive.
Visit a parse tree produced by VerilogParser#default_nettype_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDefine_directive(ctx: Define_directiveContext): T
Visit a parse tree produced by VerilogParser#define_directive.
Visit a parse tree produced by VerilogParser#define_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDefined_flag(ctx: Defined_flagContext): T
Visit a parse tree produced by VerilogParser#defined_flag.
Visit a parse tree produced by VerilogParser#defined_flag.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDelay2(ctx: Delay2Context): T
Visit a parse tree produced by VerilogParser#delay2.
Visit a parse tree produced by VerilogParser#delay2.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDelay3(ctx: Delay3Context): T
Visit a parse tree produced by VerilogParser#delay3.
Visit a parse tree produced by VerilogParser#delay3.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDelay_control(ctx: Delay_controlContext): T
Visit a parse tree produced by VerilogParser#delay_control.
Visit a parse tree produced by VerilogParser#delay_control.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDelay_or_event_control(ctx: Delay_or_event_controlContext): T
Visit a parse tree produced by VerilogParser#delay_or_event_control.
Visit a parse tree produced by VerilogParser#delay_or_event_control.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDelay_value(ctx: Delay_valueContext): T
Visit a parse tree produced by VerilogParser#delay_value.
Visit a parse tree produced by VerilogParser#delay_value.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDelayed_data(ctx: Delayed_dataContext): T
Visit a parse tree produced by VerilogParser#delayed_data.
Visit a parse tree produced by VerilogParser#delayed_data.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDelayed_reference(ctx: Delayed_referenceContext): T
Visit a parse tree produced by VerilogParser#delayed_reference.
Visit a parse tree produced by VerilogParser#delayed_reference.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDescription(ctx: DescriptionContext): T
Visit a parse tree produced by VerilogParser#description.
Visit a parse tree produced by VerilogParser#description.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDesign_statement(ctx: Design_statementContext): T
Visit a parse tree produced by VerilogParser#design_statement.
Visit a parse tree produced by VerilogParser#design_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDimension(ctx: DimensionContext): T
Visit a parse tree produced by VerilogParser#dimension.
Visit a parse tree produced by VerilogParser#dimension.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDimension_constant_expression(ctx: Dimension_constant_expressionContext): T
Visit a parse tree produced by VerilogParser#dimension_constant_expression.
Visit a parse tree produced by VerilogParser#dimension_constant_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDirective(ctx: DirectiveContext): T
Visit a parse tree produced by VerilogParser#directive.
Visit a parse tree produced by VerilogParser#directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDisable_statement(ctx: Disable_statementContext): T
Visit a parse tree produced by VerilogParser#disable_statement.
Visit a parse tree produced by VerilogParser#disable_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitDrive_strength(ctx: Drive_strengthContext): T
Visit a parse tree produced by VerilogParser#drive_strength.
Visit a parse tree produced by VerilogParser#drive_strength.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEdge_identifier(ctx: Edge_identifierContext): T
Visit a parse tree produced by VerilogParser#edge_identifier.
Visit a parse tree produced by VerilogParser#edge_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEdge_sensitive_path_declaration(ctx: Edge_sensitive_path_declarationContext): T
Visit a parse tree produced by VerilogParser#edge_sensitive_path_declaration.
Visit a parse tree produced by VerilogParser#edge_sensitive_path_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitElse_directive(ctx: Else_directiveContext): T
Visit a parse tree produced by VerilogParser#else_directive.
Visit a parse tree produced by VerilogParser#else_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitElsif_directive(ctx: Elsif_directiveContext): T
Visit a parse tree produced by VerilogParser#elsif_directive.
Visit a parse tree produced by VerilogParser#elsif_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEnable_gate_instance(ctx: Enable_gate_instanceContext): T
Visit a parse tree produced by VerilogParser#enable_gate_instance.
Visit a parse tree produced by VerilogParser#enable_gate_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEnable_gatetype(ctx: Enable_gatetypeContext): T
Visit a parse tree produced by VerilogParser#enable_gatetype.
Visit a parse tree produced by VerilogParser#enable_gatetype.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEnable_terminal(ctx: Enable_terminalContext): T
Visit a parse tree produced by VerilogParser#enable_terminal.
Visit a parse tree produced by VerilogParser#enable_terminal.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEnd_edge_offset(ctx: End_edge_offsetContext): T
Visit a parse tree produced by VerilogParser#end_edge_offset.
Visit a parse tree produced by VerilogParser#end_edge_offset.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEndif_directive(ctx: Endif_directiveContext): T
Visit a parse tree produced by VerilogParser#endif_directive.
Visit a parse tree produced by VerilogParser#endif_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitErrorNode(arg0: ErrorNode): T
Definition Classes
AbstractParseTreeVisitor → ParseTreeVisitor
def visitError_limit_value(ctx: Error_limit_valueContext): T
Visit a parse tree produced by VerilogParser#error_limit_value.
Visit a parse tree produced by VerilogParser#error_limit_value.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEscaped_arrayed_identifier(ctx: Escaped_arrayed_identifierContext): T
Visit a parse tree produced by VerilogParser#escaped_arrayed_identifier.
Visit a parse tree produced by VerilogParser#escaped_arrayed_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEscaped_hierarchical_branch(ctx: Escaped_hierarchical_branchContext): T
Visit a parse tree produced by VerilogParser#escaped_hierarchical_branch.
Visit a parse tree produced by VerilogParser#escaped_hierarchical_branch.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEscaped_hierarchical_identifier(ctx: Escaped_hierarchical_identifierContext): T
Visit a parse tree produced by VerilogParser#escaped_hierarchical_identifier.
Visit a parse tree produced by VerilogParser#escaped_hierarchical_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEvent_based_flag(ctx: Event_based_flagContext): T
Visit a parse tree produced by VerilogParser#event_based_flag.
Visit a parse tree produced by VerilogParser#event_based_flag.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEvent_control(ctx: Event_controlContext): T
Visit a parse tree produced by VerilogParser#event_control.
Visit a parse tree produced by VerilogParser#event_control.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEvent_declaration(ctx: Event_declarationContext): T
Visit a parse tree produced by VerilogParser#event_declaration.
Visit a parse tree produced by VerilogParser#event_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEvent_expression(ctx: Event_expressionContext): T
Visit a parse tree produced by VerilogParser#event_expression.
Visit a parse tree produced by VerilogParser#event_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEvent_identifier(ctx: Event_identifierContext): T
Visit a parse tree produced by VerilogParser#event_identifier.
Visit a parse tree produced by VerilogParser#event_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEvent_primary(ctx: Event_primaryContext): T
Visit a parse tree produced by VerilogParser#event_primary.
Visit a parse tree produced by VerilogParser#event_primary.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitEvent_trigger(ctx: Event_triggerContext): T
Visit a parse tree produced by VerilogParser#event_trigger.
Visit a parse tree produced by VerilogParser#event_trigger.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitExpression(ctx: ExpressionContext): T
Visit a parse tree produced by VerilogParser#expression.
Visit a parse tree produced by VerilogParser#expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFull_edge_sensitive_path_description(ctx: Full_edge_sensitive_path_descriptionContext): T
Visit a parse tree produced by VerilogParser#full_edge_sensitive_path_description.
Visit a parse tree produced by VerilogParser#full_edge_sensitive_path_description.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFull_path_description(ctx: Full_path_descriptionContext): T
Visit a parse tree produced by VerilogParser#full_path_description.
Visit a parse tree produced by VerilogParser#full_path_description.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_blocking_assignment(ctx: Function_blocking_assignmentContext): T
Visit a parse tree produced by VerilogParser#function_blocking_assignment.
Visit a parse tree produced by VerilogParser#function_blocking_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_call(ctx: Function_callContext): T
Visit a parse tree produced by VerilogParser#function_call.
Visit a parse tree produced by VerilogParser#function_call.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_case_body(ctx: Function_case_bodyContext): T
Visit a parse tree produced by VerilogParser#function_case_body.
Visit a parse tree produced by VerilogParser#function_case_body.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_case_item(ctx: Function_case_itemContext): T
Visit a parse tree produced by VerilogParser#function_case_item.
Visit a parse tree produced by VerilogParser#function_case_item.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_case_statement(ctx: Function_case_statementContext): T
Visit a parse tree produced by VerilogParser#function_case_statement.
Visit a parse tree produced by VerilogParser#function_case_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_conditional_statement(ctx: Function_conditional_statementContext): T
Visit a parse tree produced by VerilogParser#function_conditional_statement.
Visit a parse tree produced by VerilogParser#function_conditional_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_declaration(ctx: Function_declarationContext): T
Visit a parse tree produced by VerilogParser#function_declaration.
Visit a parse tree produced by VerilogParser#function_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_identifier(ctx: Function_identifierContext): T
Visit a parse tree produced by VerilogParser#function_identifier.
Visit a parse tree produced by VerilogParser#function_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_if_else_if_statement(ctx: Function_if_else_if_statementContext): T
Visit a parse tree produced by VerilogParser#function_if_else_if_statement.
Visit a parse tree produced by VerilogParser#function_if_else_if_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_item_declaration(ctx: Function_item_declarationContext): T
Visit a parse tree produced by VerilogParser#function_item_declaration.
Visit a parse tree produced by VerilogParser#function_item_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_loop_statement(ctx: Function_loop_statementContext): T
Visit a parse tree produced by VerilogParser#function_loop_statement.
Visit a parse tree produced by VerilogParser#function_loop_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_port(ctx: Function_portContext): T
Visit a parse tree produced by VerilogParser#function_port.
Visit a parse tree produced by VerilogParser#function_port.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_port_list(ctx: Function_port_listContext): T
Visit a parse tree produced by VerilogParser#function_port_list.
Visit a parse tree produced by VerilogParser#function_port_list.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_seq_block(ctx: Function_seq_blockContext): T
Visit a parse tree produced by VerilogParser#function_seq_block.
Visit a parse tree produced by VerilogParser#function_seq_block.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_statement(ctx: Function_statementContext): T
Visit a parse tree produced by VerilogParser#function_statement.
Visit a parse tree produced by VerilogParser#function_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitFunction_statement_or_null(ctx: Function_statement_or_nullContext): T
Visit a parse tree produced by VerilogParser#function_statement_or_null.
Visit a parse tree produced by VerilogParser#function_statement_or_null.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGate_instance_identifier(ctx: Gate_instance_identifierContext): T
Visit a parse tree produced by VerilogParser#gate_instance_identifier.
Visit a parse tree produced by VerilogParser#gate_instance_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGate_instantiation(ctx: Gate_instantiationContext): T
Visit a parse tree produced by VerilogParser#gate_instantiation.
Visit a parse tree produced by VerilogParser#gate_instantiation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenerate_block(ctx: Generate_blockContext): T
Visit a parse tree produced by VerilogParser#generate_block.
Visit a parse tree produced by VerilogParser#generate_block.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenerate_block_identifier(ctx: Generate_block_identifierContext): T
Visit a parse tree produced by VerilogParser#generate_block_identifier.
Visit a parse tree produced by VerilogParser#generate_block_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenerate_case_body(ctx: Generate_case_bodyContext): T
Visit a parse tree produced by VerilogParser#generate_case_body.
Visit a parse tree produced by VerilogParser#generate_case_body.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenerate_case_statement(ctx: Generate_case_statementContext): T
Visit a parse tree produced by VerilogParser#generate_case_statement.
Visit a parse tree produced by VerilogParser#generate_case_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenerate_conditional_statement(ctx: Generate_conditional_statementContext): T
Visit a parse tree produced by VerilogParser#generate_conditional_statement.
Visit a parse tree produced by VerilogParser#generate_conditional_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenerate_item(ctx: Generate_itemContext): T
Visit a parse tree produced by VerilogParser#generate_item.
Visit a parse tree produced by VerilogParser#generate_item.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenerate_item_or_null(ctx: Generate_item_or_nullContext): T
Visit a parse tree produced by VerilogParser#generate_item_or_null.
Visit a parse tree produced by VerilogParser#generate_item_or_null.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenerate_loop_statement(ctx: Generate_loop_statementContext): T
Visit a parse tree produced by VerilogParser#generate_loop_statement.
Visit a parse tree produced by VerilogParser#generate_loop_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenerated_instantiation(ctx: Generated_instantiationContext): T
Visit a parse tree produced by VerilogParser#generated_instantiation.
Visit a parse tree produced by VerilogParser#generated_instantiation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenvar_assignment(ctx: Genvar_assignmentContext): T
Visit a parse tree produced by VerilogParser#genvar_assignment.
Visit a parse tree produced by VerilogParser#genvar_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenvar_case_item(ctx: Genvar_case_itemContext): T
Visit a parse tree produced by VerilogParser#genvar_case_item.
Visit a parse tree produced by VerilogParser#genvar_case_item.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenvar_declaration(ctx: Genvar_declarationContext): T
Visit a parse tree produced by VerilogParser#genvar_declaration.
Visit a parse tree produced by VerilogParser#genvar_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenvar_function_call(ctx: Genvar_function_callContext): T
Visit a parse tree produced by VerilogParser#genvar_function_call.
Visit a parse tree produced by VerilogParser#genvar_function_call.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenvar_function_identifier(ctx: Genvar_function_identifierContext): T
Visit a parse tree produced by VerilogParser#genvar_function_identifier.
Visit a parse tree produced by VerilogParser#genvar_function_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitGenvar_identifier(ctx: Genvar_identifierContext): T
Visit a parse tree produced by VerilogParser#genvar_identifier.
Visit a parse tree produced by VerilogParser#genvar_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitHierarchical_block_identifier(ctx: Hierarchical_block_identifierContext): T
Visit a parse tree produced by VerilogParser#hierarchical_block_identifier.
Visit a parse tree produced by VerilogParser#hierarchical_block_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitHierarchical_event_identifier(ctx: Hierarchical_event_identifierContext): T
Visit a parse tree produced by VerilogParser#hierarchical_event_identifier.
Visit a parse tree produced by VerilogParser#hierarchical_event_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitHierarchical_function_identifier(ctx: Hierarchical_function_identifierContext): T
Visit a parse tree produced by VerilogParser#hierarchical_function_identifier.
Visit a parse tree produced by VerilogParser#hierarchical_function_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitHierarchical_identifier(ctx: Hierarchical_identifierContext): T
Visit a parse tree produced by VerilogParser#hierarchical_identifier.
Visit a parse tree produced by VerilogParser#hierarchical_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitHierarchical_net_identifier(ctx: Hierarchical_net_identifierContext): T
Visit a parse tree produced by VerilogParser#hierarchical_net_identifier.
Visit a parse tree produced by VerilogParser#hierarchical_net_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitHierarchical_task_identifier(ctx: Hierarchical_task_identifierContext): T
Visit a parse tree produced by VerilogParser#hierarchical_task_identifier.
Visit a parse tree produced by VerilogParser#hierarchical_task_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitHierarchical_variable_identifier(ctx: Hierarchical_variable_identifierContext): T
Visit a parse tree produced by VerilogParser#hierarchical_variable_identifier.
Visit a parse tree produced by VerilogParser#hierarchical_variable_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitIdentifier(ctx: IdentifierContext): T
Visit a parse tree produced by VerilogParser#identifier.
Visit a parse tree produced by VerilogParser#identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitIfdef_directive(ctx: Ifdef_directiveContext): T
Visit a parse tree produced by VerilogParser#ifdef_directive.
Visit a parse tree produced by VerilogParser#ifdef_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitIfndef_directive(ctx: Ifndef_directiveContext): T
Visit a parse tree produced by VerilogParser#ifndef_directive.
Visit a parse tree produced by VerilogParser#ifndef_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInclude_directive(ctx: Include_directiveContext): T
Visit a parse tree produced by VerilogParser#include_directive.
Visit a parse tree produced by VerilogParser#include_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitIncomplete_condition_statement(ctx: Incomplete_condition_statementContext): T
Visit a parse tree produced by VerilogParser#incomplete_condition_statement.
Visit a parse tree produced by VerilogParser#incomplete_condition_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitIncomplete_statement(ctx: Incomplete_statementContext): T
Visit a parse tree produced by VerilogParser#incomplete_statement.
Visit a parse tree produced by VerilogParser#incomplete_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInitial_construct(ctx: Initial_constructContext): T
Visit a parse tree produced by VerilogParser#initial_construct.
Visit a parse tree produced by VerilogParser#initial_construct.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInout_declaration(ctx: Inout_declarationContext): T
Visit a parse tree produced by VerilogParser#inout_declaration.
Visit a parse tree produced by VerilogParser#inout_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInout_port_identifier(ctx: Inout_port_identifierContext): T
Visit a parse tree produced by VerilogParser#inout_port_identifier.
Visit a parse tree produced by VerilogParser#inout_port_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInout_terminal(ctx: Inout_terminalContext): T
Visit a parse tree produced by VerilogParser#inout_terminal.
Visit a parse tree produced by VerilogParser#inout_terminal.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInput_declaration(ctx: Input_declarationContext): T
Visit a parse tree produced by VerilogParser#input_declaration.
Visit a parse tree produced by VerilogParser#input_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInput_identifier(ctx: Input_identifierContext): T
Visit a parse tree produced by VerilogParser#input_identifier.
Visit a parse tree produced by VerilogParser#input_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInput_port_identifier(ctx: Input_port_identifierContext): T
Visit a parse tree produced by VerilogParser#input_port_identifier.
Visit a parse tree produced by VerilogParser#input_port_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInput_terminal(ctx: Input_terminalContext): T
Visit a parse tree produced by VerilogParser#input_terminal.
Visit a parse tree produced by VerilogParser#input_terminal.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInst_clause(ctx: Inst_clauseContext): T
Visit a parse tree produced by VerilogParser#inst_clause.
Visit a parse tree produced by VerilogParser#inst_clause.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInst_name(ctx: Inst_nameContext): T
Visit a parse tree produced by VerilogParser#inst_name.
Visit a parse tree produced by VerilogParser#inst_name.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInstance_identifier(ctx: Instance_identifierContext): T
Visit a parse tree produced by VerilogParser#instance_identifier.
Visit a parse tree produced by VerilogParser#instance_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitInteger_declaration(ctx: Integer_declarationContext): T
Visit a parse tree produced by VerilogParser#integer_declaration.
Visit a parse tree produced by VerilogParser#integer_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitLiblist_clause(ctx: Liblist_clauseContext): T
Visit a parse tree produced by VerilogParser#liblist_clause.
Visit a parse tree produced by VerilogParser#liblist_clause.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitLibrary_identifier(ctx: Library_identifierContext): T
Visit a parse tree produced by VerilogParser#library_identifier.
Visit a parse tree produced by VerilogParser#library_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitLimit_value(ctx: Limit_valueContext): T
Visit a parse tree produced by VerilogParser#limit_value.
Visit a parse tree produced by VerilogParser#limit_value.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_block_variable_identifiers(ctx: List_of_block_variable_identifiersContext): T
Visit a parse tree produced by VerilogParser#list_of_block_variable_identifiers.
Visit a parse tree produced by VerilogParser#list_of_block_variable_identifiers.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_event_identifiers(ctx: List_of_event_identifiersContext): T
Visit a parse tree produced by VerilogParser#list_of_event_identifiers.
Visit a parse tree produced by VerilogParser#list_of_event_identifiers.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_genvar_identifiers(ctx: List_of_genvar_identifiersContext): T
Visit a parse tree produced by VerilogParser#list_of_genvar_identifiers.
Visit a parse tree produced by VerilogParser#list_of_genvar_identifiers.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_net_assignments(ctx: List_of_net_assignmentsContext): T
Visit a parse tree produced by VerilogParser#list_of_net_assignments.
Visit a parse tree produced by VerilogParser#list_of_net_assignments.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_net_decl_assignments(ctx: List_of_net_decl_assignmentsContext): T
Visit a parse tree produced by VerilogParser#list_of_net_decl_assignments.
Visit a parse tree produced by VerilogParser#list_of_net_decl_assignments.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_net_identifiers(ctx: List_of_net_identifiersContext): T
Visit a parse tree produced by VerilogParser#list_of_net_identifiers.
Visit a parse tree produced by VerilogParser#list_of_net_identifiers.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_param_assignments(ctx: List_of_param_assignmentsContext): T
Visit a parse tree produced by VerilogParser#list_of_param_assignments.
Visit a parse tree produced by VerilogParser#list_of_param_assignments.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_parameter_assignments(ctx: List_of_parameter_assignmentsContext): T
Visit a parse tree produced by VerilogParser#list_of_parameter_assignments.
Visit a parse tree produced by VerilogParser#list_of_parameter_assignments.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_path_delay_expressions(ctx: List_of_path_delay_expressionsContext): T
Visit a parse tree produced by VerilogParser#list_of_path_delay_expressions.
Visit a parse tree produced by VerilogParser#list_of_path_delay_expressions.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_path_inputs(ctx: List_of_path_inputsContext): T
Visit a parse tree produced by VerilogParser#list_of_path_inputs.
Visit a parse tree produced by VerilogParser#list_of_path_inputs.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_path_outputs(ctx: List_of_path_outputsContext): T
Visit a parse tree produced by VerilogParser#list_of_path_outputs.
Visit a parse tree produced by VerilogParser#list_of_path_outputs.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_port_connections(ctx: List_of_port_connectionsContext): T
Visit a parse tree produced by VerilogParser#list_of_port_connections.
Visit a parse tree produced by VerilogParser#list_of_port_connections.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_port_declarations(ctx: List_of_port_declarationsContext): T
Visit a parse tree produced by VerilogParser#list_of_port_declarations.
Visit a parse tree produced by VerilogParser#list_of_port_declarations.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_port_identifiers(ctx: List_of_port_identifiersContext): T
Visit a parse tree produced by VerilogParser#list_of_port_identifiers.
Visit a parse tree produced by VerilogParser#list_of_port_identifiers.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_ports(ctx: List_of_portsContext): T
Visit a parse tree produced by VerilogParser#list_of_ports.
Visit a parse tree produced by VerilogParser#list_of_ports.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_real_identifiers(ctx: List_of_real_identifiersContext): T
Visit a parse tree produced by VerilogParser#list_of_real_identifiers.
Visit a parse tree produced by VerilogParser#list_of_real_identifiers.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_specparam_assignments(ctx: List_of_specparam_assignmentsContext): T
Visit a parse tree produced by VerilogParser#list_of_specparam_assignments.
Visit a parse tree produced by VerilogParser#list_of_specparam_assignments.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_variable_identifiers(ctx: List_of_variable_identifiersContext): T
Visit a parse tree produced by VerilogParser#list_of_variable_identifiers.
Visit a parse tree produced by VerilogParser#list_of_variable_identifiers.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitList_of_variable_port_identifiers(ctx: List_of_variable_port_identifiersContext): T
Visit a parse tree produced by VerilogParser#list_of_variable_port_identifiers.
Visit a parse tree produced by VerilogParser#list_of_variable_port_identifiers.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitLocal_parameter_declaration(ctx: Local_parameter_declarationContext): T
Visit a parse tree produced by VerilogParser#local_parameter_declaration.
Visit a parse tree produced by VerilogParser#local_parameter_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitLoop_statement(ctx: Loop_statementContext): T
Visit a parse tree produced by VerilogParser#loop_statement.
Visit a parse tree produced by VerilogParser#loop_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitLsb_constant_expression(ctx: Lsb_constant_expressionContext): T
Visit a parse tree produced by VerilogParser#lsb_constant_expression.
Visit a parse tree produced by VerilogParser#lsb_constant_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitMemory_identifier(ctx: Memory_identifierContext): T
Visit a parse tree produced by VerilogParser#memory_identifier.
Visit a parse tree produced by VerilogParser#memory_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitMintypmax_expression(ctx: Mintypmax_expressionContext): T
Visit a parse tree produced by VerilogParser#mintypmax_expression.
Visit a parse tree produced by VerilogParser#mintypmax_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_declaration(ctx: Module_declarationContext): T
Visit a parse tree produced by VerilogParser#module_declaration.
Visit a parse tree produced by VerilogParser#module_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_head(ctx: Module_headContext): T
Visit a parse tree produced by VerilogParser#module_head.
Visit a parse tree produced by VerilogParser#module_head.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_identifier(ctx: Module_identifierContext): T
Visit a parse tree produced by VerilogParser#module_identifier.
Visit a parse tree produced by VerilogParser#module_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_instance(ctx: Module_instanceContext): T
Visit a parse tree produced by VerilogParser#module_instance.
Visit a parse tree produced by VerilogParser#module_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_instance_identifier(ctx: Module_instance_identifierContext): T
Visit a parse tree produced by VerilogParser#module_instance_identifier.
Visit a parse tree produced by VerilogParser#module_instance_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_instantiation(ctx: Module_instantiationContext): T
Visit a parse tree produced by VerilogParser#module_instantiation.
Visit a parse tree produced by VerilogParser#module_instantiation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_item(ctx: Module_itemContext): T
Visit a parse tree produced by VerilogParser#module_item.
Visit a parse tree produced by VerilogParser#module_item.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_keyword(ctx: Module_keywordContext): T
Visit a parse tree produced by VerilogParser#module_keyword.
Visit a parse tree produced by VerilogParser#module_keyword.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_or_generate_item(ctx: Module_or_generate_itemContext): T
Visit a parse tree produced by VerilogParser#module_or_generate_item.
Visit a parse tree produced by VerilogParser#module_or_generate_item.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_or_generate_item_declaration(ctx: Module_or_generate_item_declarationContext): T
Visit a parse tree produced by VerilogParser#module_or_generate_item_declaration.
Visit a parse tree produced by VerilogParser#module_or_generate_item_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_parameter_port_list(ctx: Module_parameter_port_listContext): T
Visit a parse tree produced by VerilogParser#module_parameter_port_list.
Visit a parse tree produced by VerilogParser#module_parameter_port_list.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_path_concatenation(ctx: Module_path_concatenationContext): T
Visit a parse tree produced by VerilogParser#module_path_concatenation.
Visit a parse tree produced by VerilogParser#module_path_concatenation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_path_conditional_expression(ctx: Module_path_conditional_expressionContext): T
Visit a parse tree produced by VerilogParser#module_path_conditional_expression.
Visit a parse tree produced by VerilogParser#module_path_conditional_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_path_expression(ctx: Module_path_expressionContext): T
Visit a parse tree produced by VerilogParser#module_path_expression.
Visit a parse tree produced by VerilogParser#module_path_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_path_mintypmax_expression(ctx: Module_path_mintypmax_expressionContext): T
Visit a parse tree produced by VerilogParser#module_path_mintypmax_expression.
Visit a parse tree produced by VerilogParser#module_path_mintypmax_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_path_multiple_concatenation(ctx: Module_path_multiple_concatenationContext): T
Visit a parse tree produced by VerilogParser#module_path_multiple_concatenation.
Visit a parse tree produced by VerilogParser#module_path_multiple_concatenation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitModule_path_primary(ctx: Module_path_primaryContext): T
Visit a parse tree produced by VerilogParser#module_path_primary.
Visit a parse tree produced by VerilogParser#module_path_primary.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitMos_switch_instance(ctx: Mos_switch_instanceContext): T
Visit a parse tree produced by VerilogParser#mos_switch_instance.
Visit a parse tree produced by VerilogParser#mos_switch_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitMos_switchtype(ctx: Mos_switchtypeContext): T
Visit a parse tree produced by VerilogParser#mos_switchtype.
Visit a parse tree produced by VerilogParser#mos_switchtype.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitMsb_constant_expression(ctx: Msb_constant_expressionContext): T
Visit a parse tree produced by VerilogParser#msb_constant_expression.
Visit a parse tree produced by VerilogParser#msb_constant_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitMultiple_concatenation(ctx: Multiple_concatenationContext): T
Visit a parse tree produced by VerilogParser#multiple_concatenation.
Visit a parse tree produced by VerilogParser#multiple_concatenation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitN_input_gate_instance(ctx: N_input_gate_instanceContext): T
Visit a parse tree produced by VerilogParser#n_input_gate_instance.
Visit a parse tree produced by VerilogParser#n_input_gate_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitN_input_gatetype(ctx: N_input_gatetypeContext): T
Visit a parse tree produced by VerilogParser#n_input_gatetype.
Visit a parse tree produced by VerilogParser#n_input_gatetype.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitN_output_gate_instance(ctx: N_output_gate_instanceContext): T
Visit a parse tree produced by VerilogParser#n_output_gate_instance.
Visit a parse tree produced by VerilogParser#n_output_gate_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitN_output_gatetype(ctx: N_output_gatetypeContext): T
Visit a parse tree produced by VerilogParser#n_output_gatetype.
Visit a parse tree produced by VerilogParser#n_output_gatetype.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitName_of_gate_instance(ctx: Name_of_gate_instanceContext): T
Visit a parse tree produced by VerilogParser#name_of_gate_instance.
Visit a parse tree produced by VerilogParser#name_of_gate_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitName_of_instance(ctx: Name_of_instanceContext): T
Visit a parse tree produced by VerilogParser#name_of_instance.
Visit a parse tree produced by VerilogParser#name_of_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNamed_parameter_assignment(ctx: Named_parameter_assignmentContext): T
Visit a parse tree produced by VerilogParser#named_parameter_assignment.
Visit a parse tree produced by VerilogParser#named_parameter_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNamed_port_connection(ctx: Named_port_connectionContext): T
Visit a parse tree produced by VerilogParser#named_port_connection.
Visit a parse tree produced by VerilogParser#named_port_connection.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNcontrol_terminal(ctx: Ncontrol_terminalContext): T
Visit a parse tree produced by VerilogParser#ncontrol_terminal.
Visit a parse tree produced by VerilogParser#ncontrol_terminal.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNet_assignment(ctx: Net_assignmentContext): T
Visit a parse tree produced by VerilogParser#net_assignment.
Visit a parse tree produced by VerilogParser#net_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNet_concatenation(ctx: Net_concatenationContext): T
Visit a parse tree produced by VerilogParser#net_concatenation.
Visit a parse tree produced by VerilogParser#net_concatenation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNet_concatenation_value(ctx: Net_concatenation_valueContext): T
Visit a parse tree produced by VerilogParser#net_concatenation_value.
Visit a parse tree produced by VerilogParser#net_concatenation_value.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNet_decl_assignment(ctx: Net_decl_assignmentContext): T
Visit a parse tree produced by VerilogParser#net_decl_assignment.
Visit a parse tree produced by VerilogParser#net_decl_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNet_declaration(ctx: Net_declarationContext): T
Visit a parse tree produced by VerilogParser#net_declaration.
Visit a parse tree produced by VerilogParser#net_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNet_identifier(ctx: Net_identifierContext): T
Visit a parse tree produced by VerilogParser#net_identifier.
Visit a parse tree produced by VerilogParser#net_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNet_lvalue(ctx: Net_lvalueContext): T
Visit a parse tree produced by VerilogParser#net_lvalue.
Visit a parse tree produced by VerilogParser#net_lvalue.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNet_type(ctx: Net_typeContext): T
Visit a parse tree produced by VerilogParser#net_type.
Visit a parse tree produced by VerilogParser#net_type.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNonblocking_assignment(ctx: Nonblocking_assignmentContext): T
Visit a parse tree produced by VerilogParser#nonblocking_assignment.
Visit a parse tree produced by VerilogParser#nonblocking_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNotify_reg(ctx: Notify_regContext): T
Visit a parse tree produced by VerilogParser#notify_reg.
Visit a parse tree produced by VerilogParser#notify_reg.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitNumber(ctx: NumberContext): T
Visit a parse tree produced by VerilogParser#number.
Visit a parse tree produced by VerilogParser#number.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitOrdered_parameter_assignment(ctx: Ordered_parameter_assignmentContext): T
Visit a parse tree produced by VerilogParser#ordered_parameter_assignment.
Visit a parse tree produced by VerilogParser#ordered_parameter_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitOrdered_port_connection(ctx: Ordered_port_connectionContext): T
Visit a parse tree produced by VerilogParser#ordered_port_connection.
Visit a parse tree produced by VerilogParser#ordered_port_connection.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitOutput_declaration(ctx: Output_declarationContext): T
Visit a parse tree produced by VerilogParser#output_declaration.
Visit a parse tree produced by VerilogParser#output_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitOutput_identifier(ctx: Output_identifierContext): T
Visit a parse tree produced by VerilogParser#output_identifier.
Visit a parse tree produced by VerilogParser#output_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitOutput_port_identifier(ctx: Output_port_identifierContext): T
Visit a parse tree produced by VerilogParser#output_port_identifier.
Visit a parse tree produced by VerilogParser#output_port_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitOutput_terminal(ctx: Output_terminalContext): T
Visit a parse tree produced by VerilogParser#output_terminal.
Visit a parse tree produced by VerilogParser#output_terminal.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitOutput_variable_type(ctx: Output_variable_typeContext): T
Visit a parse tree produced by VerilogParser#output_variable_type.
Visit a parse tree produced by VerilogParser#output_variable_type.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPar_block(ctx: Par_blockContext): T
Visit a parse tree produced by VerilogParser#par_block.
Visit a parse tree produced by VerilogParser#par_block.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitParallel_edge_sensitive_path_description(ctx: Parallel_edge_sensitive_path_descriptionContext): T
Visit a parse tree produced by VerilogParser#parallel_edge_sensitive_path_description.
Visit a parse tree produced by VerilogParser#parallel_edge_sensitive_path_description.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitParallel_path_description(ctx: Parallel_path_descriptionContext): T
Visit a parse tree produced by VerilogParser#parallel_path_description.
Visit a parse tree produced by VerilogParser#parallel_path_description.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitParam_assignment(ctx: Param_assignmentContext): T
Visit a parse tree produced by VerilogParser#param_assignment.
Visit a parse tree produced by VerilogParser#param_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitParameter_declaration(ctx: Parameter_declarationContext): T
Visit a parse tree produced by VerilogParser#parameter_declaration.
Visit a parse tree produced by VerilogParser#parameter_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitParameter_declaration_(ctx: Parameter_declaration_Context): T
Visit a parse tree produced by VerilogParser#parameter_declaration_.
Visit a parse tree produced by VerilogParser#parameter_declaration_.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitParameter_identifier(ctx: Parameter_identifierContext): T
Visit a parse tree produced by VerilogParser#parameter_identifier.
Visit a parse tree produced by VerilogParser#parameter_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitParameter_override(ctx: Parameter_overrideContext): T
Visit a parse tree produced by VerilogParser#parameter_override.
Visit a parse tree produced by VerilogParser#parameter_override.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitParameter_value_assignment(ctx: Parameter_value_assignmentContext): T
Visit a parse tree produced by VerilogParser#parameter_value_assignment.
Visit a parse tree produced by VerilogParser#parameter_value_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPass_en_switchtype(ctx: Pass_en_switchtypeContext): T
Visit a parse tree produced by VerilogParser#pass_en_switchtype.
Visit a parse tree produced by VerilogParser#pass_en_switchtype.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPass_enable_switch_instance(ctx: Pass_enable_switch_instanceContext): T
Visit a parse tree produced by VerilogParser#pass_enable_switch_instance.
Visit a parse tree produced by VerilogParser#pass_enable_switch_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPass_switch_instance(ctx: Pass_switch_instanceContext): T
Visit a parse tree produced by VerilogParser#pass_switch_instance.
Visit a parse tree produced by VerilogParser#pass_switch_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPass_switchtype(ctx: Pass_switchtypeContext): T
Visit a parse tree produced by VerilogParser#pass_switchtype.
Visit a parse tree produced by VerilogParser#pass_switchtype.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPath_declaration(ctx: Path_declarationContext): T
Visit a parse tree produced by VerilogParser#path_declaration.
Visit a parse tree produced by VerilogParser#path_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPath_delay_expression(ctx: Path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#path_delay_expression.
Visit a parse tree produced by VerilogParser#path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPath_delay_value(ctx: Path_delay_valueContext): T
Visit a parse tree produced by VerilogParser#path_delay_value.
Visit a parse tree produced by VerilogParser#path_delay_value.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPcontrol_terminal(ctx: Pcontrol_terminalContext): T
Visit a parse tree produced by VerilogParser#pcontrol_terminal.
Visit a parse tree produced by VerilogParser#pcontrol_terminal.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPolarity_operator(ctx: Polarity_operatorContext): T
Visit a parse tree produced by VerilogParser#polarity_operator.
Visit a parse tree produced by VerilogParser#polarity_operator.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPort(ctx: PortContext): T
Visit a parse tree produced by VerilogParser#port.
Visit a parse tree produced by VerilogParser#port.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPort_declaration(ctx: Port_declarationContext): T
Visit a parse tree produced by VerilogParser#port_declaration.
Visit a parse tree produced by VerilogParser#port_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPort_expression(ctx: Port_expressionContext): T
Visit a parse tree produced by VerilogParser#port_expression.
Visit a parse tree produced by VerilogParser#port_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPort_identifier(ctx: Port_identifierContext): T
Visit a parse tree produced by VerilogParser#port_identifier.
Visit a parse tree produced by VerilogParser#port_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPort_reference(ctx: Port_referenceContext): T
Visit a parse tree produced by VerilogParser#port_reference.
Visit a parse tree produced by VerilogParser#port_reference.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPrimary(ctx: PrimaryContext): T
Visit a parse tree produced by VerilogParser#primary.
Visit a parse tree produced by VerilogParser#primary.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitProcedural_continuous_assignments(ctx: Procedural_continuous_assignmentsContext): T
Visit a parse tree produced by VerilogParser#procedural_continuous_assignments.
Visit a parse tree produced by VerilogParser#procedural_continuous_assignments.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitProcedural_timing_control_statement(ctx: Procedural_timing_control_statementContext): T
Visit a parse tree produced by VerilogParser#procedural_timing_control_statement.
Visit a parse tree produced by VerilogParser#procedural_timing_control_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPull_gate_instance(ctx: Pull_gate_instanceContext): T
Visit a parse tree produced by VerilogParser#pull_gate_instance.
Visit a parse tree produced by VerilogParser#pull_gate_instance.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPulldown_strength(ctx: Pulldown_strengthContext): T
Visit a parse tree produced by VerilogParser#pulldown_strength.
Visit a parse tree produced by VerilogParser#pulldown_strength.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPullup_strength(ctx: Pullup_strengthContext): T
Visit a parse tree produced by VerilogParser#pullup_strength.
Visit a parse tree produced by VerilogParser#pullup_strength.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPulse_control_specparam(ctx: Pulse_control_specparamContext): T
Visit a parse tree produced by VerilogParser#pulse_control_specparam.
Visit a parse tree produced by VerilogParser#pulse_control_specparam.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitPulsestyle_declaration(ctx: Pulsestyle_declarationContext): T
Visit a parse tree produced by VerilogParser#pulsestyle_declaration.
Visit a parse tree produced by VerilogParser#pulsestyle_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitRange_(ctx: Range_Context): T
Visit a parse tree produced by VerilogParser#range_.
Visit a parse tree produced by VerilogParser#range_.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitRange_expression(ctx: Range_expressionContext): T
Visit a parse tree produced by VerilogParser#range_expression.
Visit a parse tree produced by VerilogParser#range_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitRange_or_type(ctx: Range_or_typeContext): T
Visit a parse tree produced by VerilogParser#range_or_type.
Visit a parse tree produced by VerilogParser#range_or_type.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitReal_declaration(ctx: Real_declarationContext): T
Visit a parse tree produced by VerilogParser#real_declaration.
Visit a parse tree produced by VerilogParser#real_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitReal_identifier(ctx: Real_identifierContext): T
Visit a parse tree produced by VerilogParser#real_identifier.
Visit a parse tree produced by VerilogParser#real_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitReal_type(ctx: Real_typeContext): T
Visit a parse tree produced by VerilogParser#real_type.
Visit a parse tree produced by VerilogParser#real_type.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitRealtime_declaration(ctx: Realtime_declarationContext): T
Visit a parse tree produced by VerilogParser#realtime_declaration.
Visit a parse tree produced by VerilogParser#realtime_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitReg_declaration(ctx: Reg_declarationContext): T
Visit a parse tree produced by VerilogParser#reg_declaration.
Visit a parse tree produced by VerilogParser#reg_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitReject_limit_value(ctx: Reject_limit_valueContext): T
Visit a parse tree produced by VerilogParser#reject_limit_value.
Visit a parse tree produced by VerilogParser#reject_limit_value.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitRemain_active_flag(ctx: Remain_active_flagContext): T
Visit a parse tree produced by VerilogParser#remain_active_flag.
Visit a parse tree produced by VerilogParser#remain_active_flag.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSeq_block(ctx: Seq_blockContext): T
Visit a parse tree produced by VerilogParser#seq_block.
Visit a parse tree produced by VerilogParser#seq_block.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitShowcancelled_declaration(ctx: Showcancelled_declarationContext): T
Visit a parse tree produced by VerilogParser#showcancelled_declaration.
Visit a parse tree produced by VerilogParser#showcancelled_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSimple_arrayed_identifier(ctx: Simple_arrayed_identifierContext): T
Visit a parse tree produced by VerilogParser#simple_arrayed_identifier.
Visit a parse tree produced by VerilogParser#simple_arrayed_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSimple_hierarchical_branch(ctx: Simple_hierarchical_branchContext): T
Visit a parse tree produced by VerilogParser#simple_hierarchical_branch.
Visit a parse tree produced by VerilogParser#simple_hierarchical_branch.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSimple_hierarchical_identifier(ctx: Simple_hierarchical_identifierContext): T
Visit a parse tree produced by VerilogParser#simple_hierarchical_identifier.
Visit a parse tree produced by VerilogParser#simple_hierarchical_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSimple_path_declaration(ctx: Simple_path_declarationContext): T
Visit a parse tree produced by VerilogParser#simple_path_declaration.
Visit a parse tree produced by VerilogParser#simple_path_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSource_text(ctx: Source_textContext): T
Visit a parse tree produced by VerilogParser#source_text.
Visit a parse tree produced by VerilogParser#source_text.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSpecify_block(ctx: Specify_blockContext): T
Visit a parse tree produced by VerilogParser#specify_block.
Visit a parse tree produced by VerilogParser#specify_block.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSpecify_input_terminal_descriptor(ctx: Specify_input_terminal_descriptorContext): T
Visit a parse tree produced by VerilogParser#specify_input_terminal_descriptor.
Visit a parse tree produced by VerilogParser#specify_input_terminal_descriptor.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSpecify_item(ctx: Specify_itemContext): T
Visit a parse tree produced by VerilogParser#specify_item.
Visit a parse tree produced by VerilogParser#specify_item.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSpecify_output_terminal_descriptor(ctx: Specify_output_terminal_descriptorContext): T
Visit a parse tree produced by VerilogParser#specify_output_terminal_descriptor.
Visit a parse tree produced by VerilogParser#specify_output_terminal_descriptor.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSpecparam_assignment(ctx: Specparam_assignmentContext): T
Visit a parse tree produced by VerilogParser#specparam_assignment.
Visit a parse tree produced by VerilogParser#specparam_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSpecparam_declaration(ctx: Specparam_declarationContext): T
Visit a parse tree produced by VerilogParser#specparam_declaration.
Visit a parse tree produced by VerilogParser#specparam_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSpecparam_identifier(ctx: Specparam_identifierContext): T
Visit a parse tree produced by VerilogParser#specparam_identifier.
Visit a parse tree produced by VerilogParser#specparam_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitStamptime_condition(ctx: Stamptime_conditionContext): T
Visit a parse tree produced by VerilogParser#stamptime_condition.
Visit a parse tree produced by VerilogParser#stamptime_condition.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitStart_edge_offset(ctx: Start_edge_offsetContext): T
Visit a parse tree produced by VerilogParser#start_edge_offset.
Visit a parse tree produced by VerilogParser#start_edge_offset.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitState_dependent_path_declaration(ctx: State_dependent_path_declarationContext): T
Visit a parse tree produced by VerilogParser#state_dependent_path_declaration.
Visit a parse tree produced by VerilogParser#state_dependent_path_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitStatement(ctx: StatementContext): T
Visit a parse tree produced by VerilogParser#statement.
Visit a parse tree produced by VerilogParser#statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitStatement_or_null(ctx: Statement_or_nullContext): T
Visit a parse tree produced by VerilogParser#statement_or_null.
Visit a parse tree produced by VerilogParser#statement_or_null.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitStrength0(ctx: Strength0Context): T
Visit a parse tree produced by VerilogParser#strength0.
Visit a parse tree produced by VerilogParser#strength0.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitStrength1(ctx: Strength1Context): T
Visit a parse tree produced by VerilogParser#strength1.
Visit a parse tree produced by VerilogParser#strength1.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSystem_function_call(ctx: System_function_callContext): T
Visit a parse tree produced by VerilogParser#system_function_call.
Visit a parse tree produced by VerilogParser#system_function_call.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSystem_function_identifier(ctx: System_function_identifierContext): T
Visit a parse tree produced by VerilogParser#system_function_identifier.
Visit a parse tree produced by VerilogParser#system_function_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSystem_task_enable(ctx: System_task_enableContext): T
Visit a parse tree produced by VerilogParser#system_task_enable.
Visit a parse tree produced by VerilogParser#system_task_enable.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitSystem_task_identifier(ctx: System_task_identifierContext): T
Visit a parse tree produced by VerilogParser#system_task_identifier.
Visit a parse tree produced by VerilogParser#system_task_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitT01_path_delay_expression(ctx: T01_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#t01_path_delay_expression.
Visit a parse tree produced by VerilogParser#t01_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitT0x_path_delay_expression(ctx: T0x_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#t0x_path_delay_expression.
Visit a parse tree produced by VerilogParser#t0x_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitT0z_path_delay_expression(ctx: T0z_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#t0z_path_delay_expression.
Visit a parse tree produced by VerilogParser#t0z_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitT10_path_delay_expression(ctx: T10_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#t10_path_delay_expression.
Visit a parse tree produced by VerilogParser#t10_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitT1x_path_delay_expression(ctx: T1x_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#t1x_path_delay_expression.
Visit a parse tree produced by VerilogParser#t1x_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitT1z_path_delay_expression(ctx: T1z_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#t1z_path_delay_expression.
Visit a parse tree produced by VerilogParser#t1z_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitT_path_delay_expression(ctx: T_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#t_path_delay_expression.
Visit a parse tree produced by VerilogParser#t_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTask_declaration(ctx: Task_declarationContext): T
Visit a parse tree produced by VerilogParser#task_declaration.
Visit a parse tree produced by VerilogParser#task_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTask_enable(ctx: Task_enableContext): T
Visit a parse tree produced by VerilogParser#task_enable.
Visit a parse tree produced by VerilogParser#task_enable.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTask_identifier(ctx: Task_identifierContext): T
Visit a parse tree produced by VerilogParser#task_identifier.
Visit a parse tree produced by VerilogParser#task_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTask_item_declaration(ctx: Task_item_declarationContext): T
Visit a parse tree produced by VerilogParser#task_item_declaration.
Visit a parse tree produced by VerilogParser#task_item_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTask_port_item(ctx: Task_port_itemContext): T
Visit a parse tree produced by VerilogParser#task_port_item.
Visit a parse tree produced by VerilogParser#task_port_item.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTask_port_list(ctx: Task_port_listContext): T
Visit a parse tree produced by VerilogParser#task_port_list.
Visit a parse tree produced by VerilogParser#task_port_list.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTask_port_type(ctx: Task_port_typeContext): T
Visit a parse tree produced by VerilogParser#task_port_type.
Visit a parse tree produced by VerilogParser#task_port_type.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTerm(ctx: TermContext): T
Visit a parse tree produced by VerilogParser#term.
Visit a parse tree produced by VerilogParser#term.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTerminal(arg0: TerminalNode): T
Definition Classes
AbstractParseTreeVisitor → ParseTreeVisitor
def visitTerminal_identifier(ctx: Terminal_identifierContext): T
Visit a parse tree produced by VerilogParser#terminal_identifier.
Visit a parse tree produced by VerilogParser#terminal_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitText_macro_identifier(ctx: Text_macro_identifierContext): T
Visit a parse tree produced by VerilogParser#text_macro_identifier.
Visit a parse tree produced by VerilogParser#text_macro_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTf_decl_header(ctx: Tf_decl_headerContext): T
Visit a parse tree produced by VerilogParser#tf_decl_header.
Visit a parse tree produced by VerilogParser#tf_decl_header.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTf_declaration(ctx: Tf_declarationContext): T
Visit a parse tree produced by VerilogParser#tf_declaration.
Visit a parse tree produced by VerilogParser#tf_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTfall_path_delay_expression(ctx: Tfall_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#tfall_path_delay_expression.
Visit a parse tree produced by VerilogParser#tfall_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitThreshold(ctx: ThresholdContext): T
Visit a parse tree produced by VerilogParser#threshold.
Visit a parse tree produced by VerilogParser#threshold.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTime_declaration(ctx: Time_declarationContext): T
Visit a parse tree produced by VerilogParser#time_declaration.
Visit a parse tree produced by VerilogParser#time_declaration.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTimescale_directive(ctx: Timescale_directiveContext): T
Visit a parse tree produced by VerilogParser#timescale_directive.
Visit a parse tree produced by VerilogParser#timescale_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTiming_check_limit(ctx: Timing_check_limitContext): T
Visit a parse tree produced by VerilogParser#timing_check_limit.
Visit a parse tree produced by VerilogParser#timing_check_limit.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTopmodule_identifier(ctx: Topmodule_identifierContext): T
Visit a parse tree produced by VerilogParser#topmodule_identifier.
Visit a parse tree produced by VerilogParser#topmodule_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTrise_path_delay_expression(ctx: Trise_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#trise_path_delay_expression.
Visit a parse tree produced by VerilogParser#trise_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTx0_path_delay_expression(ctx: Tx0_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#tx0_path_delay_expression.
Visit a parse tree produced by VerilogParser#tx0_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTx1_path_delay_expression(ctx: Tx1_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#tx1_path_delay_expression.
Visit a parse tree produced by VerilogParser#tx1_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTxz_path_delay_expression(ctx: Txz_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#txz_path_delay_expression.
Visit a parse tree produced by VerilogParser#txz_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTz0_path_delay_expression(ctx: Tz0_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#tz0_path_delay_expression.
Visit a parse tree produced by VerilogParser#tz0_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTz1_path_delay_expression(ctx: Tz1_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#tz1_path_delay_expression.
Visit a parse tree produced by VerilogParser#tz1_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTz_path_delay_expression(ctx: Tz_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#tz_path_delay_expression.
Visit a parse tree produced by VerilogParser#tz_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitTzx_path_delay_expression(ctx: Tzx_path_delay_expressionContext): T
Visit a parse tree produced by VerilogParser#tzx_path_delay_expression.
Visit a parse tree produced by VerilogParser#tzx_path_delay_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitUdp_identifier(ctx: Udp_identifierContext): T
Visit a parse tree produced by VerilogParser#udp_identifier.
Visit a parse tree produced by VerilogParser#udp_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitUdp_instance_identifier(ctx: Udp_instance_identifierContext): T
Visit a parse tree produced by VerilogParser#udp_instance_identifier.
Visit a parse tree produced by VerilogParser#udp_instance_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitUnary_module_path_operator(ctx: Unary_module_path_operatorContext): T
Visit a parse tree produced by VerilogParser#unary_module_path_operator.
Visit a parse tree produced by VerilogParser#unary_module_path_operator.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitUnary_operator(ctx: Unary_operatorContext): T
Visit a parse tree produced by VerilogParser#unary_operator.
Visit a parse tree produced by VerilogParser#unary_operator.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitUndef_directive(ctx: Undef_directiveContext): T
Visit a parse tree produced by VerilogParser#undef_directive.
Visit a parse tree produced by VerilogParser#undef_directive.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitUse_clause(ctx: Use_clauseContext): T
Visit a parse tree produced by VerilogParser#use_clause.
Visit a parse tree produced by VerilogParser#use_clause.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitUsing_defined_flag(ctx: Using_defined_flagContext): T
Visit a parse tree produced by VerilogParser#using_defined_flag.
Visit a parse tree produced by VerilogParser#using_defined_flag.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitVariable_assignment(ctx: Variable_assignmentContext): T
Visit a parse tree produced by VerilogParser#variable_assignment.
Visit a parse tree produced by VerilogParser#variable_assignment.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitVariable_concatenation(ctx: Variable_concatenationContext): T
Visit a parse tree produced by VerilogParser#variable_concatenation.
Visit a parse tree produced by VerilogParser#variable_concatenation.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitVariable_concatenation_value(ctx: Variable_concatenation_valueContext): T
Visit a parse tree produced by VerilogParser#variable_concatenation_value.
Visit a parse tree produced by VerilogParser#variable_concatenation_value.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitVariable_identifier(ctx: Variable_identifierContext): T
Visit a parse tree produced by VerilogParser#variable_identifier.
Visit a parse tree produced by VerilogParser#variable_identifier.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitVariable_lvalue(ctx: Variable_lvalueContext): T
Visit a parse tree produced by VerilogParser#variable_lvalue.
Visit a parse tree produced by VerilogParser#variable_lvalue.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitVariable_type(ctx: Variable_typeContext): T
Visit a parse tree produced by VerilogParser#variable_type.
Visit a parse tree produced by VerilogParser#variable_type.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitWait_statement(ctx: Wait_statementContext): T
Visit a parse tree produced by VerilogParser#wait_statement.
Visit a parse tree produced by VerilogParser#wait_statement.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
def visitWidth_constant_expression(ctx: Width_constant_expressionContext): T
Visit a parse tree produced by VerilogParser#width_constant_expression.
Visit a parse tree produced by VerilogParser#width_constant_expression.
The default implementation returns the result of calling #visitChildren on ctx.
ctx
the parse tree
returns
the visitor result
Definition Classes
VerilogParserBaseVisitor → VerilogParserVisitor
Annotations
@Override()
final def wait(arg0: Long, arg1: Int): Unit
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.InterruptedException])
final def wait(arg0: Long): Unit
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.InterruptedException]) @native()
final def wait(): Unit
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.InterruptedException])

Deprecated Value Members

def finalize(): Unit
Attributes
protected[lang]
Definition Classes
AnyRef
Annotations
@throws(classOf[java.lang.Throwable]) @Deprecated
Deprecated
(Since version 9)

Packages

VerilogParserBaseVisitor

class VerilogParserBaseVisitor[T] extends AbstractParseTreeVisitor[T] with VerilogParserVisitor[T]

Instance Constructors

Value Members

Deprecated Value Members

Inherited from VerilogParserVisitor[T]

Inherited from AbstractParseTreeVisitor[T]

Inherited from ParseTreeVisitor[T]

Inherited from AnyRef

Inherited from Any

Ungrouped

Packages

VerilogParserBaseVisitor

class VerilogParserBaseVisitor[T] extends AbstractParseTreeVisitor[T] with VerilogParserVisitor[T]

Instance Constructors

Value Members

Deprecated Value Members

Inherited from VerilogParserVisitor[T]

Inherited from AbstractParseTreeVisitor[T]

Inherited from ParseTreeVisitor[T]

Inherited from AnyRef

Inherited from Any

Ungrouped

VerilogParserBaseVisitor