VerilogParserListener

trait VerilogParserListener extends ParseTreeListener

This interface defines a complete listener for a parse tree produced by VerilogParser.

Linear Supertypes

ParseTreeListener, AnyRef, Any

Known Subclasses

VerilogParserBaseListener

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Inherited

VerilogParserListener
ParseTreeListener
AnyRef
Any

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Visibility

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Protected

Abstract Value Members

abstract def enterAlways_construct(ctx: Always_constructContext): Unit
Enter a parse tree produced by VerilogParser#always_construct.
Enter a parse tree produced by VerilogParser#always_construct.
ctx
the parse tree
abstract def enterArrayed_identifier(ctx: Arrayed_identifierContext): Unit
Enter a parse tree produced by VerilogParser#arrayed_identifier.
Enter a parse tree produced by VerilogParser#arrayed_identifier.
ctx
the parse tree
abstract def enterAttr_name(ctx: Attr_nameContext): Unit
Enter a parse tree produced by VerilogParser#attr_name.
Enter a parse tree produced by VerilogParser#attr_name.
ctx
the parse tree
abstract def enterAttr_spec(ctx: Attr_specContext): Unit
Enter a parse tree produced by VerilogParser#attr_spec.
Enter a parse tree produced by VerilogParser#attr_spec.
ctx
the parse tree
abstract def enterAttribute_instance(ctx: Attribute_instanceContext): Unit
Enter a parse tree produced by VerilogParser#attribute_instance.
Enter a parse tree produced by VerilogParser#attribute_instance.
ctx
the parse tree
abstract def enterBase_expression(ctx: Base_expressionContext): Unit
Enter a parse tree produced by VerilogParser#base_expression.
Enter a parse tree produced by VerilogParser#base_expression.
ctx
the parse tree
abstract def enterBinary_module_path_operator(ctx: Binary_module_path_operatorContext): Unit
Enter a parse tree produced by VerilogParser#binary_module_path_operator.
Enter a parse tree produced by VerilogParser#binary_module_path_operator.
ctx
the parse tree
abstract def enterBinary_operator(ctx: Binary_operatorContext): Unit
Enter a parse tree produced by VerilogParser#binary_operator.
Enter a parse tree produced by VerilogParser#binary_operator.
ctx
the parse tree
abstract def enterBinary_operator_or(ctx: Binary_operator_orContext): Unit
Enter a parse tree produced by VerilogParser#binary_operator_or.
Enter a parse tree produced by VerilogParser#binary_operator_or.
ctx
the parse tree
abstract def enterBlock_identifier(ctx: Block_identifierContext): Unit
Enter a parse tree produced by VerilogParser#block_identifier.
Enter a parse tree produced by VerilogParser#block_identifier.
ctx
the parse tree
abstract def enterBlock_item_declaration(ctx: Block_item_declarationContext): Unit
Enter a parse tree produced by VerilogParser#block_item_declaration.
Enter a parse tree produced by VerilogParser#block_item_declaration.
ctx
the parse tree
abstract def enterBlock_reg_declaration(ctx: Block_reg_declarationContext): Unit
Enter a parse tree produced by VerilogParser#block_reg_declaration.
Enter a parse tree produced by VerilogParser#block_reg_declaration.
ctx
the parse tree
abstract def enterBlock_variable_type(ctx: Block_variable_typeContext): Unit
Enter a parse tree produced by VerilogParser#block_variable_type.
Enter a parse tree produced by VerilogParser#block_variable_type.
ctx
the parse tree
abstract def enterBlocking_assignment(ctx: Blocking_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#blocking_assignment.
Enter a parse tree produced by VerilogParser#blocking_assignment.
ctx
the parse tree
abstract def enterCase_body(ctx: Case_bodyContext): Unit
Enter a parse tree produced by VerilogParser#case_body.
Enter a parse tree produced by VerilogParser#case_body.
ctx
the parse tree
abstract def enterCase_default_item(ctx: Case_default_itemContext): Unit
Enter a parse tree produced by VerilogParser#case_default_item.
Enter a parse tree produced by VerilogParser#case_default_item.
ctx
the parse tree
abstract def enterCase_item(ctx: Case_itemContext): Unit
Enter a parse tree produced by VerilogParser#case_item.
Enter a parse tree produced by VerilogParser#case_item.
ctx
the parse tree
abstract def enterCase_statement(ctx: Case_statementContext): Unit
Enter a parse tree produced by VerilogParser#case_statement.
Enter a parse tree produced by VerilogParser#case_statement.
ctx
the parse tree
abstract def enterCell_clause(ctx: Cell_clauseContext): Unit
Enter a parse tree produced by VerilogParser#cell_clause.
Enter a parse tree produced by VerilogParser#cell_clause.
ctx
the parse tree
abstract def enterCell_identifier(ctx: Cell_identifierContext): Unit
Enter a parse tree produced by VerilogParser#cell_identifier.
Enter a parse tree produced by VerilogParser#cell_identifier.
ctx
the parse tree
abstract def enterCharge_strength(ctx: Charge_strengthContext): Unit
Enter a parse tree produced by VerilogParser#charge_strength.
Enter a parse tree produced by VerilogParser#charge_strength.
ctx
the parse tree
abstract def enterChecktime_condition(ctx: Checktime_conditionContext): Unit
Enter a parse tree produced by VerilogParser#checktime_condition.
Enter a parse tree produced by VerilogParser#checktime_condition.
ctx
the parse tree
abstract def enterCmos_switch_instance(ctx: Cmos_switch_instanceContext): Unit
Enter a parse tree produced by VerilogParser#cmos_switch_instance.
Enter a parse tree produced by VerilogParser#cmos_switch_instance.
ctx
the parse tree
abstract def enterCmos_switchtype(ctx: Cmos_switchtypeContext): Unit
Enter a parse tree produced by VerilogParser#cmos_switchtype.
Enter a parse tree produced by VerilogParser#cmos_switchtype.
ctx
the parse tree
abstract def enterConcatenation(ctx: ConcatenationContext): Unit
Enter a parse tree produced by VerilogParser#concatenation.
Enter a parse tree produced by VerilogParser#concatenation.
ctx
the parse tree
abstract def enterConditional_statement(ctx: Conditional_statementContext): Unit
Enter a parse tree produced by VerilogParser#conditional_statement.
Enter a parse tree produced by VerilogParser#conditional_statement.
ctx
the parse tree
abstract def enterConditional_statement_body(ctx: Conditional_statement_bodyContext): Unit
Enter a parse tree produced by VerilogParser#conditional_statement_body.
Enter a parse tree produced by VerilogParser#conditional_statement_body.
ctx
the parse tree
abstract def enterConditional_statement_chain(ctx: Conditional_statement_chainContext): Unit
Enter a parse tree produced by VerilogParser#conditional_statement_chain.
Enter a parse tree produced by VerilogParser#conditional_statement_chain.
ctx
the parse tree
abstract def enterConditional_statement_else_chain(ctx: Conditional_statement_else_chainContext): Unit
Enter a parse tree produced by VerilogParser#conditional_statement_else_chain.
Enter a parse tree produced by VerilogParser#conditional_statement_else_chain.
ctx
the parse tree
abstract def enterConditional_statement_else_tail(ctx: Conditional_statement_else_tailContext): Unit
Enter a parse tree produced by VerilogParser#conditional_statement_else_tail.
Enter a parse tree produced by VerilogParser#conditional_statement_else_tail.
ctx
the parse tree
abstract def enterConditional_statement_head(ctx: Conditional_statement_headContext): Unit
Enter a parse tree produced by VerilogParser#conditional_statement_head.
Enter a parse tree produced by VerilogParser#conditional_statement_head.
ctx
the parse tree
abstract def enterConfig_declaration(ctx: Config_declarationContext): Unit
Enter a parse tree produced by VerilogParser#config_declaration.
Enter a parse tree produced by VerilogParser#config_declaration.
ctx
the parse tree
abstract def enterConfig_identifier(ctx: Config_identifierContext): Unit
Enter a parse tree produced by VerilogParser#config_identifier.
Enter a parse tree produced by VerilogParser#config_identifier.
ctx
the parse tree
abstract def enterConfig_rule_statement(ctx: Config_rule_statementContext): Unit
Enter a parse tree produced by VerilogParser#config_rule_statement.
Enter a parse tree produced by VerilogParser#config_rule_statement.
ctx
the parse tree
abstract def enterConstant_base_expression(ctx: Constant_base_expressionContext): Unit
Enter a parse tree produced by VerilogParser#constant_base_expression.
Enter a parse tree produced by VerilogParser#constant_base_expression.
ctx
the parse tree
abstract def enterConstant_concatenation(ctx: Constant_concatenationContext): Unit
Enter a parse tree produced by VerilogParser#constant_concatenation.
Enter a parse tree produced by VerilogParser#constant_concatenation.
ctx
the parse tree
abstract def enterConstant_expression(ctx: Constant_expressionContext): Unit
Enter a parse tree produced by VerilogParser#constant_expression.
Enter a parse tree produced by VerilogParser#constant_expression.
ctx
the parse tree
abstract def enterConstant_function_call(ctx: Constant_function_callContext): Unit
Enter a parse tree produced by VerilogParser#constant_function_call.
Enter a parse tree produced by VerilogParser#constant_function_call.
ctx
the parse tree
abstract def enterConstant_mintypmax_expression(ctx: Constant_mintypmax_expressionContext): Unit
Enter a parse tree produced by VerilogParser#constant_mintypmax_expression.
Enter a parse tree produced by VerilogParser#constant_mintypmax_expression.
ctx
the parse tree
abstract def enterConstant_multiple_concatenation(ctx: Constant_multiple_concatenationContext): Unit
Enter a parse tree produced by VerilogParser#constant_multiple_concatenation.
Enter a parse tree produced by VerilogParser#constant_multiple_concatenation.
ctx
the parse tree
abstract def enterConstant_primary(ctx: Constant_primaryContext): Unit
Enter a parse tree produced by VerilogParser#constant_primary.
Enter a parse tree produced by VerilogParser#constant_primary.
ctx
the parse tree
abstract def enterConstant_range_expression(ctx: Constant_range_expressionContext): Unit
Enter a parse tree produced by VerilogParser#constant_range_expression.
Enter a parse tree produced by VerilogParser#constant_range_expression.
ctx
the parse tree
abstract def enterContinuous_assign(ctx: Continuous_assignContext): Unit
Enter a parse tree produced by VerilogParser#continuous_assign.
Enter a parse tree produced by VerilogParser#continuous_assign.
ctx
the parse tree
abstract def enterCreate_defined_flag(ctx: Create_defined_flagContext): Unit
Enter a parse tree produced by VerilogParser#create_defined_flag.
Enter a parse tree produced by VerilogParser#create_defined_flag.
ctx
the parse tree
abstract def enterCreate_defined_term(ctx: Create_defined_termContext): Unit
Enter a parse tree produced by VerilogParser#create_defined_term.
Enter a parse tree produced by VerilogParser#create_defined_term.
ctx
the parse tree
abstract def enterData_source_expression(ctx: Data_source_expressionContext): Unit
Enter a parse tree produced by VerilogParser#data_source_expression.
Enter a parse tree produced by VerilogParser#data_source_expression.
ctx
the parse tree
abstract def enterDefault_clause(ctx: Default_clauseContext): Unit
Enter a parse tree produced by VerilogParser#default_clause.
Enter a parse tree produced by VerilogParser#default_clause.
ctx
the parse tree
abstract def enterDefault_nettype_directive(ctx: Default_nettype_directiveContext): Unit
Enter a parse tree produced by VerilogParser#default_nettype_directive.
Enter a parse tree produced by VerilogParser#default_nettype_directive.
ctx
the parse tree
abstract def enterDefine_directive(ctx: Define_directiveContext): Unit
Enter a parse tree produced by VerilogParser#define_directive.
Enter a parse tree produced by VerilogParser#define_directive.
ctx
the parse tree
abstract def enterDefined_flag(ctx: Defined_flagContext): Unit
Enter a parse tree produced by VerilogParser#defined_flag.
Enter a parse tree produced by VerilogParser#defined_flag.
ctx
the parse tree
abstract def enterDelay2(ctx: Delay2Context): Unit
Enter a parse tree produced by VerilogParser#delay2.
Enter a parse tree produced by VerilogParser#delay2.
ctx
the parse tree
abstract def enterDelay3(ctx: Delay3Context): Unit
Enter a parse tree produced by VerilogParser#delay3.
Enter a parse tree produced by VerilogParser#delay3.
ctx
the parse tree
abstract def enterDelay_control(ctx: Delay_controlContext): Unit
Enter a parse tree produced by VerilogParser#delay_control.
Enter a parse tree produced by VerilogParser#delay_control.
ctx
the parse tree
abstract def enterDelay_or_event_control(ctx: Delay_or_event_controlContext): Unit
Enter a parse tree produced by VerilogParser#delay_or_event_control.
Enter a parse tree produced by VerilogParser#delay_or_event_control.
ctx
the parse tree
abstract def enterDelay_value(ctx: Delay_valueContext): Unit
Enter a parse tree produced by VerilogParser#delay_value.
Enter a parse tree produced by VerilogParser#delay_value.
ctx
the parse tree
abstract def enterDelayed_data(ctx: Delayed_dataContext): Unit
Enter a parse tree produced by VerilogParser#delayed_data.
Enter a parse tree produced by VerilogParser#delayed_data.
ctx
the parse tree
abstract def enterDelayed_reference(ctx: Delayed_referenceContext): Unit
Enter a parse tree produced by VerilogParser#delayed_reference.
Enter a parse tree produced by VerilogParser#delayed_reference.
ctx
the parse tree
abstract def enterDescription(ctx: DescriptionContext): Unit
Enter a parse tree produced by VerilogParser#description.
Enter a parse tree produced by VerilogParser#description.
ctx
the parse tree
abstract def enterDesign_statement(ctx: Design_statementContext): Unit
Enter a parse tree produced by VerilogParser#design_statement.
Enter a parse tree produced by VerilogParser#design_statement.
ctx
the parse tree
abstract def enterDimension(ctx: DimensionContext): Unit
Enter a parse tree produced by VerilogParser#dimension.
Enter a parse tree produced by VerilogParser#dimension.
ctx
the parse tree
abstract def enterDimension_constant_expression(ctx: Dimension_constant_expressionContext): Unit
Enter a parse tree produced by VerilogParser#dimension_constant_expression.
Enter a parse tree produced by VerilogParser#dimension_constant_expression.
ctx
the parse tree
abstract def enterDirective(ctx: DirectiveContext): Unit
Enter a parse tree produced by VerilogParser#directive.
Enter a parse tree produced by VerilogParser#directive.
ctx
the parse tree
abstract def enterDisable_statement(ctx: Disable_statementContext): Unit
Enter a parse tree produced by VerilogParser#disable_statement.
Enter a parse tree produced by VerilogParser#disable_statement.
ctx
the parse tree
abstract def enterDrive_strength(ctx: Drive_strengthContext): Unit
Enter a parse tree produced by VerilogParser#drive_strength.
Enter a parse tree produced by VerilogParser#drive_strength.
ctx
the parse tree
abstract def enterEdge_identifier(ctx: Edge_identifierContext): Unit
Enter a parse tree produced by VerilogParser#edge_identifier.
Enter a parse tree produced by VerilogParser#edge_identifier.
ctx
the parse tree
abstract def enterEdge_sensitive_path_declaration(ctx: Edge_sensitive_path_declarationContext): Unit
Enter a parse tree produced by VerilogParser#edge_sensitive_path_declaration.
Enter a parse tree produced by VerilogParser#edge_sensitive_path_declaration.
ctx
the parse tree
abstract def enterElse_directive(ctx: Else_directiveContext): Unit
Enter a parse tree produced by VerilogParser#else_directive.
Enter a parse tree produced by VerilogParser#else_directive.
ctx
the parse tree
abstract def enterElsif_directive(ctx: Elsif_directiveContext): Unit
Enter a parse tree produced by VerilogParser#elsif_directive.
Enter a parse tree produced by VerilogParser#elsif_directive.
ctx
the parse tree
abstract def enterEnable_gate_instance(ctx: Enable_gate_instanceContext): Unit
Enter a parse tree produced by VerilogParser#enable_gate_instance.
Enter a parse tree produced by VerilogParser#enable_gate_instance.
ctx
the parse tree
abstract def enterEnable_gatetype(ctx: Enable_gatetypeContext): Unit
Enter a parse tree produced by VerilogParser#enable_gatetype.
Enter a parse tree produced by VerilogParser#enable_gatetype.
ctx
the parse tree
abstract def enterEnable_terminal(ctx: Enable_terminalContext): Unit
Enter a parse tree produced by VerilogParser#enable_terminal.
Enter a parse tree produced by VerilogParser#enable_terminal.
ctx
the parse tree
abstract def enterEnd_edge_offset(ctx: End_edge_offsetContext): Unit
Enter a parse tree produced by VerilogParser#end_edge_offset.
Enter a parse tree produced by VerilogParser#end_edge_offset.
ctx
the parse tree
abstract def enterEndif_directive(ctx: Endif_directiveContext): Unit
Enter a parse tree produced by VerilogParser#endif_directive.
Enter a parse tree produced by VerilogParser#endif_directive.
ctx
the parse tree
abstract def enterError_limit_value(ctx: Error_limit_valueContext): Unit
Enter a parse tree produced by VerilogParser#error_limit_value.
Enter a parse tree produced by VerilogParser#error_limit_value.
ctx
the parse tree
abstract def enterEscaped_arrayed_identifier(ctx: Escaped_arrayed_identifierContext): Unit
Enter a parse tree produced by VerilogParser#escaped_arrayed_identifier.
Enter a parse tree produced by VerilogParser#escaped_arrayed_identifier.
ctx
the parse tree
abstract def enterEscaped_hierarchical_branch(ctx: Escaped_hierarchical_branchContext): Unit
Enter a parse tree produced by VerilogParser#escaped_hierarchical_branch.
Enter a parse tree produced by VerilogParser#escaped_hierarchical_branch.
ctx
the parse tree
abstract def enterEscaped_hierarchical_identifier(ctx: Escaped_hierarchical_identifierContext): Unit
Enter a parse tree produced by VerilogParser#escaped_hierarchical_identifier.
Enter a parse tree produced by VerilogParser#escaped_hierarchical_identifier.
ctx
the parse tree
abstract def enterEvent_based_flag(ctx: Event_based_flagContext): Unit
Enter a parse tree produced by VerilogParser#event_based_flag.
Enter a parse tree produced by VerilogParser#event_based_flag.
ctx
the parse tree
abstract def enterEvent_control(ctx: Event_controlContext): Unit
Enter a parse tree produced by VerilogParser#event_control.
Enter a parse tree produced by VerilogParser#event_control.
ctx
the parse tree
abstract def enterEvent_declaration(ctx: Event_declarationContext): Unit
Enter a parse tree produced by VerilogParser#event_declaration.
Enter a parse tree produced by VerilogParser#event_declaration.
ctx
the parse tree
abstract def enterEvent_expression(ctx: Event_expressionContext): Unit
Enter a parse tree produced by VerilogParser#event_expression.
Enter a parse tree produced by VerilogParser#event_expression.
ctx
the parse tree
abstract def enterEvent_identifier(ctx: Event_identifierContext): Unit
Enter a parse tree produced by VerilogParser#event_identifier.
Enter a parse tree produced by VerilogParser#event_identifier.
ctx
the parse tree
abstract def enterEvent_primary(ctx: Event_primaryContext): Unit
Enter a parse tree produced by VerilogParser#event_primary.
Enter a parse tree produced by VerilogParser#event_primary.
ctx
the parse tree
abstract def enterEvent_trigger(ctx: Event_triggerContext): Unit
Enter a parse tree produced by VerilogParser#event_trigger.
Enter a parse tree produced by VerilogParser#event_trigger.
ctx
the parse tree
abstract def enterEveryRule(arg0: ParserRuleContext): Unit
Definition Classes
ParseTreeListener
abstract def enterExpression(ctx: ExpressionContext): Unit
Enter a parse tree produced by VerilogParser#expression.
Enter a parse tree produced by VerilogParser#expression.
ctx
the parse tree
abstract def enterFull_edge_sensitive_path_description(ctx: Full_edge_sensitive_path_descriptionContext): Unit
Enter a parse tree produced by VerilogParser#full_edge_sensitive_path_description.
Enter a parse tree produced by VerilogParser#full_edge_sensitive_path_description.
ctx
the parse tree
abstract def enterFull_path_description(ctx: Full_path_descriptionContext): Unit
Enter a parse tree produced by VerilogParser#full_path_description.
Enter a parse tree produced by VerilogParser#full_path_description.
ctx
the parse tree
abstract def enterFunction_blocking_assignment(ctx: Function_blocking_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#function_blocking_assignment.
Enter a parse tree produced by VerilogParser#function_blocking_assignment.
ctx
the parse tree
abstract def enterFunction_call(ctx: Function_callContext): Unit
Enter a parse tree produced by VerilogParser#function_call.
Enter a parse tree produced by VerilogParser#function_call.
ctx
the parse tree
abstract def enterFunction_case_body(ctx: Function_case_bodyContext): Unit
Enter a parse tree produced by VerilogParser#function_case_body.
Enter a parse tree produced by VerilogParser#function_case_body.
ctx
the parse tree
abstract def enterFunction_case_item(ctx: Function_case_itemContext): Unit
Enter a parse tree produced by VerilogParser#function_case_item.
Enter a parse tree produced by VerilogParser#function_case_item.
ctx
the parse tree
abstract def enterFunction_case_statement(ctx: Function_case_statementContext): Unit
Enter a parse tree produced by VerilogParser#function_case_statement.
Enter a parse tree produced by VerilogParser#function_case_statement.
ctx
the parse tree
abstract def enterFunction_conditional_statement(ctx: Function_conditional_statementContext): Unit
Enter a parse tree produced by VerilogParser#function_conditional_statement.
Enter a parse tree produced by VerilogParser#function_conditional_statement.
ctx
the parse tree
abstract def enterFunction_declaration(ctx: Function_declarationContext): Unit
Enter a parse tree produced by VerilogParser#function_declaration.
Enter a parse tree produced by VerilogParser#function_declaration.
ctx
the parse tree
abstract def enterFunction_identifier(ctx: Function_identifierContext): Unit
Enter a parse tree produced by VerilogParser#function_identifier.
Enter a parse tree produced by VerilogParser#function_identifier.
ctx
the parse tree
abstract def enterFunction_if_else_if_statement(ctx: Function_if_else_if_statementContext): Unit
Enter a parse tree produced by VerilogParser#function_if_else_if_statement.
Enter a parse tree produced by VerilogParser#function_if_else_if_statement.
ctx
the parse tree
abstract def enterFunction_item_declaration(ctx: Function_item_declarationContext): Unit
Enter a parse tree produced by VerilogParser#function_item_declaration.
Enter a parse tree produced by VerilogParser#function_item_declaration.
ctx
the parse tree
abstract def enterFunction_loop_statement(ctx: Function_loop_statementContext): Unit
Enter a parse tree produced by VerilogParser#function_loop_statement.
Enter a parse tree produced by VerilogParser#function_loop_statement.
ctx
the parse tree
abstract def enterFunction_port(ctx: Function_portContext): Unit
Enter a parse tree produced by VerilogParser#function_port.
Enter a parse tree produced by VerilogParser#function_port.
ctx
the parse tree
abstract def enterFunction_port_list(ctx: Function_port_listContext): Unit
Enter a parse tree produced by VerilogParser#function_port_list.
Enter a parse tree produced by VerilogParser#function_port_list.
ctx
the parse tree
abstract def enterFunction_seq_block(ctx: Function_seq_blockContext): Unit
Enter a parse tree produced by VerilogParser#function_seq_block.
Enter a parse tree produced by VerilogParser#function_seq_block.
ctx
the parse tree
abstract def enterFunction_statement(ctx: Function_statementContext): Unit
Enter a parse tree produced by VerilogParser#function_statement.
Enter a parse tree produced by VerilogParser#function_statement.
ctx
the parse tree
abstract def enterFunction_statement_or_null(ctx: Function_statement_or_nullContext): Unit
Enter a parse tree produced by VerilogParser#function_statement_or_null.
Enter a parse tree produced by VerilogParser#function_statement_or_null.
ctx
the parse tree
abstract def enterGate_instance_identifier(ctx: Gate_instance_identifierContext): Unit
Enter a parse tree produced by VerilogParser#gate_instance_identifier.
Enter a parse tree produced by VerilogParser#gate_instance_identifier.
ctx
the parse tree
abstract def enterGate_instantiation(ctx: Gate_instantiationContext): Unit
Enter a parse tree produced by VerilogParser#gate_instantiation.
Enter a parse tree produced by VerilogParser#gate_instantiation.
ctx
the parse tree
abstract def enterGenerate_block(ctx: Generate_blockContext): Unit
Enter a parse tree produced by VerilogParser#generate_block.
Enter a parse tree produced by VerilogParser#generate_block.
ctx
the parse tree
abstract def enterGenerate_block_identifier(ctx: Generate_block_identifierContext): Unit
Enter a parse tree produced by VerilogParser#generate_block_identifier.
Enter a parse tree produced by VerilogParser#generate_block_identifier.
ctx
the parse tree
abstract def enterGenerate_case_body(ctx: Generate_case_bodyContext): Unit
Enter a parse tree produced by VerilogParser#generate_case_body.
Enter a parse tree produced by VerilogParser#generate_case_body.
ctx
the parse tree
abstract def enterGenerate_case_statement(ctx: Generate_case_statementContext): Unit
Enter a parse tree produced by VerilogParser#generate_case_statement.
Enter a parse tree produced by VerilogParser#generate_case_statement.
ctx
the parse tree
abstract def enterGenerate_conditional_statement(ctx: Generate_conditional_statementContext): Unit
Enter a parse tree produced by VerilogParser#generate_conditional_statement.
Enter a parse tree produced by VerilogParser#generate_conditional_statement.
ctx
the parse tree
abstract def enterGenerate_item(ctx: Generate_itemContext): Unit
Enter a parse tree produced by VerilogParser#generate_item.
Enter a parse tree produced by VerilogParser#generate_item.
ctx
the parse tree
abstract def enterGenerate_item_or_null(ctx: Generate_item_or_nullContext): Unit
Enter a parse tree produced by VerilogParser#generate_item_or_null.
Enter a parse tree produced by VerilogParser#generate_item_or_null.
ctx
the parse tree
abstract def enterGenerate_loop_statement(ctx: Generate_loop_statementContext): Unit
Enter a parse tree produced by VerilogParser#generate_loop_statement.
Enter a parse tree produced by VerilogParser#generate_loop_statement.
ctx
the parse tree
abstract def enterGenerated_instantiation(ctx: Generated_instantiationContext): Unit
Enter a parse tree produced by VerilogParser#generated_instantiation.
Enter a parse tree produced by VerilogParser#generated_instantiation.
ctx
the parse tree
abstract def enterGenvar_assignment(ctx: Genvar_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#genvar_assignment.
Enter a parse tree produced by VerilogParser#genvar_assignment.
ctx
the parse tree
abstract def enterGenvar_case_item(ctx: Genvar_case_itemContext): Unit
Enter a parse tree produced by VerilogParser#genvar_case_item.
Enter a parse tree produced by VerilogParser#genvar_case_item.
ctx
the parse tree
abstract def enterGenvar_declaration(ctx: Genvar_declarationContext): Unit
Enter a parse tree produced by VerilogParser#genvar_declaration.
Enter a parse tree produced by VerilogParser#genvar_declaration.
ctx
the parse tree
abstract def enterGenvar_function_call(ctx: Genvar_function_callContext): Unit
Enter a parse tree produced by VerilogParser#genvar_function_call.
Enter a parse tree produced by VerilogParser#genvar_function_call.
ctx
the parse tree
abstract def enterGenvar_function_identifier(ctx: Genvar_function_identifierContext): Unit
Enter a parse tree produced by VerilogParser#genvar_function_identifier.
Enter a parse tree produced by VerilogParser#genvar_function_identifier.
ctx
the parse tree
abstract def enterGenvar_identifier(ctx: Genvar_identifierContext): Unit
Enter a parse tree produced by VerilogParser#genvar_identifier.
Enter a parse tree produced by VerilogParser#genvar_identifier.
ctx
the parse tree
abstract def enterHierarchical_block_identifier(ctx: Hierarchical_block_identifierContext): Unit
Enter a parse tree produced by VerilogParser#hierarchical_block_identifier.
Enter a parse tree produced by VerilogParser#hierarchical_block_identifier.
ctx
the parse tree
abstract def enterHierarchical_event_identifier(ctx: Hierarchical_event_identifierContext): Unit
Enter a parse tree produced by VerilogParser#hierarchical_event_identifier.
Enter a parse tree produced by VerilogParser#hierarchical_event_identifier.
ctx
the parse tree
abstract def enterHierarchical_function_identifier(ctx: Hierarchical_function_identifierContext): Unit
Enter a parse tree produced by VerilogParser#hierarchical_function_identifier.
Enter a parse tree produced by VerilogParser#hierarchical_function_identifier.
ctx
the parse tree
abstract def enterHierarchical_identifier(ctx: Hierarchical_identifierContext): Unit
Enter a parse tree produced by VerilogParser#hierarchical_identifier.
Enter a parse tree produced by VerilogParser#hierarchical_identifier.
ctx
the parse tree
abstract def enterHierarchical_net_identifier(ctx: Hierarchical_net_identifierContext): Unit
Enter a parse tree produced by VerilogParser#hierarchical_net_identifier.
Enter a parse tree produced by VerilogParser#hierarchical_net_identifier.
ctx
the parse tree
abstract def enterHierarchical_task_identifier(ctx: Hierarchical_task_identifierContext): Unit
Enter a parse tree produced by VerilogParser#hierarchical_task_identifier.
Enter a parse tree produced by VerilogParser#hierarchical_task_identifier.
ctx
the parse tree
abstract def enterHierarchical_variable_identifier(ctx: Hierarchical_variable_identifierContext): Unit
Enter a parse tree produced by VerilogParser#hierarchical_variable_identifier.
Enter a parse tree produced by VerilogParser#hierarchical_variable_identifier.
ctx
the parse tree
abstract def enterIdentifier(ctx: IdentifierContext): Unit
Enter a parse tree produced by VerilogParser#identifier.
Enter a parse tree produced by VerilogParser#identifier.
ctx
the parse tree
abstract def enterIfdef_directive(ctx: Ifdef_directiveContext): Unit
Enter a parse tree produced by VerilogParser#ifdef_directive.
Enter a parse tree produced by VerilogParser#ifdef_directive.
ctx
the parse tree
abstract def enterIfndef_directive(ctx: Ifndef_directiveContext): Unit
Enter a parse tree produced by VerilogParser#ifndef_directive.
Enter a parse tree produced by VerilogParser#ifndef_directive.
ctx
the parse tree
abstract def enterInclude_directive(ctx: Include_directiveContext): Unit
Enter a parse tree produced by VerilogParser#include_directive.
Enter a parse tree produced by VerilogParser#include_directive.
ctx
the parse tree
abstract def enterIncomplete_condition_statement(ctx: Incomplete_condition_statementContext): Unit
Enter a parse tree produced by VerilogParser#incomplete_condition_statement.
Enter a parse tree produced by VerilogParser#incomplete_condition_statement.
ctx
the parse tree
abstract def enterIncomplete_statement(ctx: Incomplete_statementContext): Unit
Enter a parse tree produced by VerilogParser#incomplete_statement.
Enter a parse tree produced by VerilogParser#incomplete_statement.
ctx
the parse tree
abstract def enterInitial_construct(ctx: Initial_constructContext): Unit
Enter a parse tree produced by VerilogParser#initial_construct.
Enter a parse tree produced by VerilogParser#initial_construct.
ctx
the parse tree
abstract def enterInout_declaration(ctx: Inout_declarationContext): Unit
Enter a parse tree produced by VerilogParser#inout_declaration.
Enter a parse tree produced by VerilogParser#inout_declaration.
ctx
the parse tree
abstract def enterInout_port_identifier(ctx: Inout_port_identifierContext): Unit
Enter a parse tree produced by VerilogParser#inout_port_identifier.
Enter a parse tree produced by VerilogParser#inout_port_identifier.
ctx
the parse tree
abstract def enterInout_terminal(ctx: Inout_terminalContext): Unit
Enter a parse tree produced by VerilogParser#inout_terminal.
Enter a parse tree produced by VerilogParser#inout_terminal.
ctx
the parse tree
abstract def enterInput_declaration(ctx: Input_declarationContext): Unit
Enter a parse tree produced by VerilogParser#input_declaration.
Enter a parse tree produced by VerilogParser#input_declaration.
ctx
the parse tree
abstract def enterInput_identifier(ctx: Input_identifierContext): Unit
Enter a parse tree produced by VerilogParser#input_identifier.
Enter a parse tree produced by VerilogParser#input_identifier.
ctx
the parse tree
abstract def enterInput_port_identifier(ctx: Input_port_identifierContext): Unit
Enter a parse tree produced by VerilogParser#input_port_identifier.
Enter a parse tree produced by VerilogParser#input_port_identifier.
ctx
the parse tree
abstract def enterInput_terminal(ctx: Input_terminalContext): Unit
Enter a parse tree produced by VerilogParser#input_terminal.
Enter a parse tree produced by VerilogParser#input_terminal.
ctx
the parse tree
abstract def enterInst_clause(ctx: Inst_clauseContext): Unit
Enter a parse tree produced by VerilogParser#inst_clause.
Enter a parse tree produced by VerilogParser#inst_clause.
ctx
the parse tree
abstract def enterInst_name(ctx: Inst_nameContext): Unit
Enter a parse tree produced by VerilogParser#inst_name.
Enter a parse tree produced by VerilogParser#inst_name.
ctx
the parse tree
abstract def enterInstance_identifier(ctx: Instance_identifierContext): Unit
Enter a parse tree produced by VerilogParser#instance_identifier.
Enter a parse tree produced by VerilogParser#instance_identifier.
ctx
the parse tree
abstract def enterInteger_declaration(ctx: Integer_declarationContext): Unit
Enter a parse tree produced by VerilogParser#integer_declaration.
Enter a parse tree produced by VerilogParser#integer_declaration.
ctx
the parse tree
abstract def enterLiblist_clause(ctx: Liblist_clauseContext): Unit
Enter a parse tree produced by VerilogParser#liblist_clause.
Enter a parse tree produced by VerilogParser#liblist_clause.
ctx
the parse tree
abstract def enterLibrary_identifier(ctx: Library_identifierContext): Unit
Enter a parse tree produced by VerilogParser#library_identifier.
Enter a parse tree produced by VerilogParser#library_identifier.
ctx
the parse tree
abstract def enterLimit_value(ctx: Limit_valueContext): Unit
Enter a parse tree produced by VerilogParser#limit_value.
Enter a parse tree produced by VerilogParser#limit_value.
ctx
the parse tree
abstract def enterList_of_block_variable_identifiers(ctx: List_of_block_variable_identifiersContext): Unit
Enter a parse tree produced by VerilogParser#list_of_block_variable_identifiers.
Enter a parse tree produced by VerilogParser#list_of_block_variable_identifiers.
ctx
the parse tree
abstract def enterList_of_event_identifiers(ctx: List_of_event_identifiersContext): Unit
Enter a parse tree produced by VerilogParser#list_of_event_identifiers.
Enter a parse tree produced by VerilogParser#list_of_event_identifiers.
ctx
the parse tree
abstract def enterList_of_genvar_identifiers(ctx: List_of_genvar_identifiersContext): Unit
Enter a parse tree produced by VerilogParser#list_of_genvar_identifiers.
Enter a parse tree produced by VerilogParser#list_of_genvar_identifiers.
ctx
the parse tree
abstract def enterList_of_net_assignments(ctx: List_of_net_assignmentsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_net_assignments.
Enter a parse tree produced by VerilogParser#list_of_net_assignments.
ctx
the parse tree
abstract def enterList_of_net_decl_assignments(ctx: List_of_net_decl_assignmentsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_net_decl_assignments.
Enter a parse tree produced by VerilogParser#list_of_net_decl_assignments.
ctx
the parse tree
abstract def enterList_of_net_identifiers(ctx: List_of_net_identifiersContext): Unit
Enter a parse tree produced by VerilogParser#list_of_net_identifiers.
Enter a parse tree produced by VerilogParser#list_of_net_identifiers.
ctx
the parse tree
abstract def enterList_of_param_assignments(ctx: List_of_param_assignmentsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_param_assignments.
Enter a parse tree produced by VerilogParser#list_of_param_assignments.
ctx
the parse tree
abstract def enterList_of_parameter_assignments(ctx: List_of_parameter_assignmentsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_parameter_assignments.
Enter a parse tree produced by VerilogParser#list_of_parameter_assignments.
ctx
the parse tree
abstract def enterList_of_path_delay_expressions(ctx: List_of_path_delay_expressionsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_path_delay_expressions.
Enter a parse tree produced by VerilogParser#list_of_path_delay_expressions.
ctx
the parse tree
abstract def enterList_of_path_inputs(ctx: List_of_path_inputsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_path_inputs.
Enter a parse tree produced by VerilogParser#list_of_path_inputs.
ctx
the parse tree
abstract def enterList_of_path_outputs(ctx: List_of_path_outputsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_path_outputs.
Enter a parse tree produced by VerilogParser#list_of_path_outputs.
ctx
the parse tree
abstract def enterList_of_port_connections(ctx: List_of_port_connectionsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_port_connections.
Enter a parse tree produced by VerilogParser#list_of_port_connections.
ctx
the parse tree
abstract def enterList_of_port_declarations(ctx: List_of_port_declarationsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_port_declarations.
Enter a parse tree produced by VerilogParser#list_of_port_declarations.
ctx
the parse tree
abstract def enterList_of_port_identifiers(ctx: List_of_port_identifiersContext): Unit
Enter a parse tree produced by VerilogParser#list_of_port_identifiers.
Enter a parse tree produced by VerilogParser#list_of_port_identifiers.
ctx
the parse tree
abstract def enterList_of_ports(ctx: List_of_portsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_ports.
Enter a parse tree produced by VerilogParser#list_of_ports.
ctx
the parse tree
abstract def enterList_of_real_identifiers(ctx: List_of_real_identifiersContext): Unit
Enter a parse tree produced by VerilogParser#list_of_real_identifiers.
Enter a parse tree produced by VerilogParser#list_of_real_identifiers.
ctx
the parse tree
abstract def enterList_of_specparam_assignments(ctx: List_of_specparam_assignmentsContext): Unit
Enter a parse tree produced by VerilogParser#list_of_specparam_assignments.
Enter a parse tree produced by VerilogParser#list_of_specparam_assignments.
ctx
the parse tree
abstract def enterList_of_variable_identifiers(ctx: List_of_variable_identifiersContext): Unit
Enter a parse tree produced by VerilogParser#list_of_variable_identifiers.
Enter a parse tree produced by VerilogParser#list_of_variable_identifiers.
ctx
the parse tree
abstract def enterList_of_variable_port_identifiers(ctx: List_of_variable_port_identifiersContext): Unit
Enter a parse tree produced by VerilogParser#list_of_variable_port_identifiers.
Enter a parse tree produced by VerilogParser#list_of_variable_port_identifiers.
ctx
the parse tree
abstract def enterLocal_parameter_declaration(ctx: Local_parameter_declarationContext): Unit
Enter a parse tree produced by VerilogParser#local_parameter_declaration.
Enter a parse tree produced by VerilogParser#local_parameter_declaration.
ctx
the parse tree
abstract def enterLoop_statement(ctx: Loop_statementContext): Unit
Enter a parse tree produced by VerilogParser#loop_statement.
Enter a parse tree produced by VerilogParser#loop_statement.
ctx
the parse tree
abstract def enterLsb_constant_expression(ctx: Lsb_constant_expressionContext): Unit
Enter a parse tree produced by VerilogParser#lsb_constant_expression.
Enter a parse tree produced by VerilogParser#lsb_constant_expression.
ctx
the parse tree
abstract def enterMemory_identifier(ctx: Memory_identifierContext): Unit
Enter a parse tree produced by VerilogParser#memory_identifier.
Enter a parse tree produced by VerilogParser#memory_identifier.
ctx
the parse tree
abstract def enterMintypmax_expression(ctx: Mintypmax_expressionContext): Unit
Enter a parse tree produced by VerilogParser#mintypmax_expression.
Enter a parse tree produced by VerilogParser#mintypmax_expression.
ctx
the parse tree
abstract def enterModule_declaration(ctx: Module_declarationContext): Unit
Enter a parse tree produced by VerilogParser#module_declaration.
Enter a parse tree produced by VerilogParser#module_declaration.
ctx
the parse tree
abstract def enterModule_head(ctx: Module_headContext): Unit
Enter a parse tree produced by VerilogParser#module_head.
Enter a parse tree produced by VerilogParser#module_head.
ctx
the parse tree
abstract def enterModule_identifier(ctx: Module_identifierContext): Unit
Enter a parse tree produced by VerilogParser#module_identifier.
Enter a parse tree produced by VerilogParser#module_identifier.
ctx
the parse tree
abstract def enterModule_instance(ctx: Module_instanceContext): Unit
Enter a parse tree produced by VerilogParser#module_instance.
Enter a parse tree produced by VerilogParser#module_instance.
ctx
the parse tree
abstract def enterModule_instance_identifier(ctx: Module_instance_identifierContext): Unit
Enter a parse tree produced by VerilogParser#module_instance_identifier.
Enter a parse tree produced by VerilogParser#module_instance_identifier.
ctx
the parse tree
abstract def enterModule_instantiation(ctx: Module_instantiationContext): Unit
Enter a parse tree produced by VerilogParser#module_instantiation.
Enter a parse tree produced by VerilogParser#module_instantiation.
ctx
the parse tree
abstract def enterModule_item(ctx: Module_itemContext): Unit
Enter a parse tree produced by VerilogParser#module_item.
Enter a parse tree produced by VerilogParser#module_item.
ctx
the parse tree
abstract def enterModule_keyword(ctx: Module_keywordContext): Unit
Enter a parse tree produced by VerilogParser#module_keyword.
Enter a parse tree produced by VerilogParser#module_keyword.
ctx
the parse tree
abstract def enterModule_or_generate_item(ctx: Module_or_generate_itemContext): Unit
Enter a parse tree produced by VerilogParser#module_or_generate_item.
Enter a parse tree produced by VerilogParser#module_or_generate_item.
ctx
the parse tree
abstract def enterModule_or_generate_item_declaration(ctx: Module_or_generate_item_declarationContext): Unit
Enter a parse tree produced by VerilogParser#module_or_generate_item_declaration.
Enter a parse tree produced by VerilogParser#module_or_generate_item_declaration.
ctx
the parse tree
abstract def enterModule_parameter_port_list(ctx: Module_parameter_port_listContext): Unit
Enter a parse tree produced by VerilogParser#module_parameter_port_list.
Enter a parse tree produced by VerilogParser#module_parameter_port_list.
ctx
the parse tree
abstract def enterModule_path_concatenation(ctx: Module_path_concatenationContext): Unit
Enter a parse tree produced by VerilogParser#module_path_concatenation.
Enter a parse tree produced by VerilogParser#module_path_concatenation.
ctx
the parse tree
abstract def enterModule_path_conditional_expression(ctx: Module_path_conditional_expressionContext): Unit
Enter a parse tree produced by VerilogParser#module_path_conditional_expression.
Enter a parse tree produced by VerilogParser#module_path_conditional_expression.
ctx
the parse tree
abstract def enterModule_path_expression(ctx: Module_path_expressionContext): Unit
Enter a parse tree produced by VerilogParser#module_path_expression.
Enter a parse tree produced by VerilogParser#module_path_expression.
ctx
the parse tree
abstract def enterModule_path_mintypmax_expression(ctx: Module_path_mintypmax_expressionContext): Unit
Enter a parse tree produced by VerilogParser#module_path_mintypmax_expression.
Enter a parse tree produced by VerilogParser#module_path_mintypmax_expression.
ctx
the parse tree
abstract def enterModule_path_multiple_concatenation(ctx: Module_path_multiple_concatenationContext): Unit
Enter a parse tree produced by VerilogParser#module_path_multiple_concatenation.
Enter a parse tree produced by VerilogParser#module_path_multiple_concatenation.
ctx
the parse tree
abstract def enterModule_path_primary(ctx: Module_path_primaryContext): Unit
Enter a parse tree produced by VerilogParser#module_path_primary.
Enter a parse tree produced by VerilogParser#module_path_primary.
ctx
the parse tree
abstract def enterMos_switch_instance(ctx: Mos_switch_instanceContext): Unit
Enter a parse tree produced by VerilogParser#mos_switch_instance.
Enter a parse tree produced by VerilogParser#mos_switch_instance.
ctx
the parse tree
abstract def enterMos_switchtype(ctx: Mos_switchtypeContext): Unit
Enter a parse tree produced by VerilogParser#mos_switchtype.
Enter a parse tree produced by VerilogParser#mos_switchtype.
ctx
the parse tree
abstract def enterMsb_constant_expression(ctx: Msb_constant_expressionContext): Unit
Enter a parse tree produced by VerilogParser#msb_constant_expression.
Enter a parse tree produced by VerilogParser#msb_constant_expression.
ctx
the parse tree
abstract def enterMultiple_concatenation(ctx: Multiple_concatenationContext): Unit
Enter a parse tree produced by VerilogParser#multiple_concatenation.
Enter a parse tree produced by VerilogParser#multiple_concatenation.
ctx
the parse tree
abstract def enterN_input_gate_instance(ctx: N_input_gate_instanceContext): Unit
Enter a parse tree produced by VerilogParser#n_input_gate_instance.
Enter a parse tree produced by VerilogParser#n_input_gate_instance.
ctx
the parse tree
abstract def enterN_input_gatetype(ctx: N_input_gatetypeContext): Unit
Enter a parse tree produced by VerilogParser#n_input_gatetype.
Enter a parse tree produced by VerilogParser#n_input_gatetype.
ctx
the parse tree
abstract def enterN_output_gate_instance(ctx: N_output_gate_instanceContext): Unit
Enter a parse tree produced by VerilogParser#n_output_gate_instance.
Enter a parse tree produced by VerilogParser#n_output_gate_instance.
ctx
the parse tree
abstract def enterN_output_gatetype(ctx: N_output_gatetypeContext): Unit
Enter a parse tree produced by VerilogParser#n_output_gatetype.
Enter a parse tree produced by VerilogParser#n_output_gatetype.
ctx
the parse tree
abstract def enterName_of_gate_instance(ctx: Name_of_gate_instanceContext): Unit
Enter a parse tree produced by VerilogParser#name_of_gate_instance.
Enter a parse tree produced by VerilogParser#name_of_gate_instance.
ctx
the parse tree
abstract def enterName_of_instance(ctx: Name_of_instanceContext): Unit
Enter a parse tree produced by VerilogParser#name_of_instance.
Enter a parse tree produced by VerilogParser#name_of_instance.
ctx
the parse tree
abstract def enterNamed_parameter_assignment(ctx: Named_parameter_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#named_parameter_assignment.
Enter a parse tree produced by VerilogParser#named_parameter_assignment.
ctx
the parse tree
abstract def enterNamed_port_connection(ctx: Named_port_connectionContext): Unit
Enter a parse tree produced by VerilogParser#named_port_connection.
Enter a parse tree produced by VerilogParser#named_port_connection.
ctx
the parse tree
abstract def enterNcontrol_terminal(ctx: Ncontrol_terminalContext): Unit
Enter a parse tree produced by VerilogParser#ncontrol_terminal.
Enter a parse tree produced by VerilogParser#ncontrol_terminal.
ctx
the parse tree
abstract def enterNet_assignment(ctx: Net_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#net_assignment.
Enter a parse tree produced by VerilogParser#net_assignment.
ctx
the parse tree
abstract def enterNet_concatenation(ctx: Net_concatenationContext): Unit
Enter a parse tree produced by VerilogParser#net_concatenation.
Enter a parse tree produced by VerilogParser#net_concatenation.
ctx
the parse tree
abstract def enterNet_concatenation_value(ctx: Net_concatenation_valueContext): Unit
Enter a parse tree produced by VerilogParser#net_concatenation_value.
Enter a parse tree produced by VerilogParser#net_concatenation_value.
ctx
the parse tree
abstract def enterNet_decl_assignment(ctx: Net_decl_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#net_decl_assignment.
Enter a parse tree produced by VerilogParser#net_decl_assignment.
ctx
the parse tree
abstract def enterNet_declaration(ctx: Net_declarationContext): Unit
Enter a parse tree produced by VerilogParser#net_declaration.
Enter a parse tree produced by VerilogParser#net_declaration.
ctx
the parse tree
abstract def enterNet_identifier(ctx: Net_identifierContext): Unit
Enter a parse tree produced by VerilogParser#net_identifier.
Enter a parse tree produced by VerilogParser#net_identifier.
ctx
the parse tree
abstract def enterNet_lvalue(ctx: Net_lvalueContext): Unit
Enter a parse tree produced by VerilogParser#net_lvalue.
Enter a parse tree produced by VerilogParser#net_lvalue.
ctx
the parse tree
abstract def enterNet_type(ctx: Net_typeContext): Unit
Enter a parse tree produced by VerilogParser#net_type.
Enter a parse tree produced by VerilogParser#net_type.
ctx
the parse tree
abstract def enterNonblocking_assignment(ctx: Nonblocking_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#nonblocking_assignment.
Enter a parse tree produced by VerilogParser#nonblocking_assignment.
ctx
the parse tree
abstract def enterNotify_reg(ctx: Notify_regContext): Unit
Enter a parse tree produced by VerilogParser#notify_reg.
Enter a parse tree produced by VerilogParser#notify_reg.
ctx
the parse tree
abstract def enterNumber(ctx: NumberContext): Unit
Enter a parse tree produced by VerilogParser#number.
Enter a parse tree produced by VerilogParser#number.
ctx
the parse tree
abstract def enterOrdered_parameter_assignment(ctx: Ordered_parameter_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#ordered_parameter_assignment.
Enter a parse tree produced by VerilogParser#ordered_parameter_assignment.
ctx
the parse tree
abstract def enterOrdered_port_connection(ctx: Ordered_port_connectionContext): Unit
Enter a parse tree produced by VerilogParser#ordered_port_connection.
Enter a parse tree produced by VerilogParser#ordered_port_connection.
ctx
the parse tree
abstract def enterOutput_declaration(ctx: Output_declarationContext): Unit
Enter a parse tree produced by VerilogParser#output_declaration.
Enter a parse tree produced by VerilogParser#output_declaration.
ctx
the parse tree
abstract def enterOutput_identifier(ctx: Output_identifierContext): Unit
Enter a parse tree produced by VerilogParser#output_identifier.
Enter a parse tree produced by VerilogParser#output_identifier.
ctx
the parse tree
abstract def enterOutput_port_identifier(ctx: Output_port_identifierContext): Unit
Enter a parse tree produced by VerilogParser#output_port_identifier.
Enter a parse tree produced by VerilogParser#output_port_identifier.
ctx
the parse tree
abstract def enterOutput_terminal(ctx: Output_terminalContext): Unit
Enter a parse tree produced by VerilogParser#output_terminal.
Enter a parse tree produced by VerilogParser#output_terminal.
ctx
the parse tree
abstract def enterOutput_variable_type(ctx: Output_variable_typeContext): Unit
Enter a parse tree produced by VerilogParser#output_variable_type.
Enter a parse tree produced by VerilogParser#output_variable_type.
ctx
the parse tree
abstract def enterPar_block(ctx: Par_blockContext): Unit
Enter a parse tree produced by VerilogParser#par_block.
Enter a parse tree produced by VerilogParser#par_block.
ctx
the parse tree
abstract def enterParallel_edge_sensitive_path_description(ctx: Parallel_edge_sensitive_path_descriptionContext): Unit
Enter a parse tree produced by VerilogParser#parallel_edge_sensitive_path_description.
Enter a parse tree produced by VerilogParser#parallel_edge_sensitive_path_description.
ctx
the parse tree
abstract def enterParallel_path_description(ctx: Parallel_path_descriptionContext): Unit
Enter a parse tree produced by VerilogParser#parallel_path_description.
Enter a parse tree produced by VerilogParser#parallel_path_description.
ctx
the parse tree
abstract def enterParam_assignment(ctx: Param_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#param_assignment.
Enter a parse tree produced by VerilogParser#param_assignment.
ctx
the parse tree
abstract def enterParameter_declaration(ctx: Parameter_declarationContext): Unit
Enter a parse tree produced by VerilogParser#parameter_declaration.
Enter a parse tree produced by VerilogParser#parameter_declaration.
ctx
the parse tree
abstract def enterParameter_declaration_(ctx: Parameter_declaration_Context): Unit
Enter a parse tree produced by VerilogParser#parameter_declaration_.
Enter a parse tree produced by VerilogParser#parameter_declaration_.
ctx
the parse tree
abstract def enterParameter_identifier(ctx: Parameter_identifierContext): Unit
Enter a parse tree produced by VerilogParser#parameter_identifier.
Enter a parse tree produced by VerilogParser#parameter_identifier.
ctx
the parse tree
abstract def enterParameter_override(ctx: Parameter_overrideContext): Unit
Enter a parse tree produced by VerilogParser#parameter_override.
Enter a parse tree produced by VerilogParser#parameter_override.
ctx
the parse tree
abstract def enterParameter_value_assignment(ctx: Parameter_value_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#parameter_value_assignment.
Enter a parse tree produced by VerilogParser#parameter_value_assignment.
ctx
the parse tree
abstract def enterPass_en_switchtype(ctx: Pass_en_switchtypeContext): Unit
Enter a parse tree produced by VerilogParser#pass_en_switchtype.
Enter a parse tree produced by VerilogParser#pass_en_switchtype.
ctx
the parse tree
abstract def enterPass_enable_switch_instance(ctx: Pass_enable_switch_instanceContext): Unit
Enter a parse tree produced by VerilogParser#pass_enable_switch_instance.
Enter a parse tree produced by VerilogParser#pass_enable_switch_instance.
ctx
the parse tree
abstract def enterPass_switch_instance(ctx: Pass_switch_instanceContext): Unit
Enter a parse tree produced by VerilogParser#pass_switch_instance.
Enter a parse tree produced by VerilogParser#pass_switch_instance.
ctx
the parse tree
abstract def enterPass_switchtype(ctx: Pass_switchtypeContext): Unit
Enter a parse tree produced by VerilogParser#pass_switchtype.
Enter a parse tree produced by VerilogParser#pass_switchtype.
ctx
the parse tree
abstract def enterPath_declaration(ctx: Path_declarationContext): Unit
Enter a parse tree produced by VerilogParser#path_declaration.
Enter a parse tree produced by VerilogParser#path_declaration.
ctx
the parse tree
abstract def enterPath_delay_expression(ctx: Path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#path_delay_expression.
Enter a parse tree produced by VerilogParser#path_delay_expression.
ctx
the parse tree
abstract def enterPath_delay_value(ctx: Path_delay_valueContext): Unit
Enter a parse tree produced by VerilogParser#path_delay_value.
Enter a parse tree produced by VerilogParser#path_delay_value.
ctx
the parse tree
abstract def enterPcontrol_terminal(ctx: Pcontrol_terminalContext): Unit
Enter a parse tree produced by VerilogParser#pcontrol_terminal.
Enter a parse tree produced by VerilogParser#pcontrol_terminal.
ctx
the parse tree
abstract def enterPolarity_operator(ctx: Polarity_operatorContext): Unit
Enter a parse tree produced by VerilogParser#polarity_operator.
Enter a parse tree produced by VerilogParser#polarity_operator.
ctx
the parse tree
abstract def enterPort(ctx: PortContext): Unit
Enter a parse tree produced by VerilogParser#port.
Enter a parse tree produced by VerilogParser#port.
ctx
the parse tree
abstract def enterPort_declaration(ctx: Port_declarationContext): Unit
Enter a parse tree produced by VerilogParser#port_declaration.
Enter a parse tree produced by VerilogParser#port_declaration.
ctx
the parse tree
abstract def enterPort_expression(ctx: Port_expressionContext): Unit
Enter a parse tree produced by VerilogParser#port_expression.
Enter a parse tree produced by VerilogParser#port_expression.
ctx
the parse tree
abstract def enterPort_identifier(ctx: Port_identifierContext): Unit
Enter a parse tree produced by VerilogParser#port_identifier.
Enter a parse tree produced by VerilogParser#port_identifier.
ctx
the parse tree
abstract def enterPort_reference(ctx: Port_referenceContext): Unit
Enter a parse tree produced by VerilogParser#port_reference.
Enter a parse tree produced by VerilogParser#port_reference.
ctx
the parse tree
abstract def enterPrimary(ctx: PrimaryContext): Unit
Enter a parse tree produced by VerilogParser#primary.
Enter a parse tree produced by VerilogParser#primary.
ctx
the parse tree
abstract def enterProcedural_continuous_assignments(ctx: Procedural_continuous_assignmentsContext): Unit
Enter a parse tree produced by VerilogParser#procedural_continuous_assignments.
Enter a parse tree produced by VerilogParser#procedural_continuous_assignments.
ctx
the parse tree
abstract def enterProcedural_timing_control_statement(ctx: Procedural_timing_control_statementContext): Unit
Enter a parse tree produced by VerilogParser#procedural_timing_control_statement.
Enter a parse tree produced by VerilogParser#procedural_timing_control_statement.
ctx
the parse tree
abstract def enterPull_gate_instance(ctx: Pull_gate_instanceContext): Unit
Enter a parse tree produced by VerilogParser#pull_gate_instance.
Enter a parse tree produced by VerilogParser#pull_gate_instance.
ctx
the parse tree
abstract def enterPulldown_strength(ctx: Pulldown_strengthContext): Unit
Enter a parse tree produced by VerilogParser#pulldown_strength.
Enter a parse tree produced by VerilogParser#pulldown_strength.
ctx
the parse tree
abstract def enterPullup_strength(ctx: Pullup_strengthContext): Unit
Enter a parse tree produced by VerilogParser#pullup_strength.
Enter a parse tree produced by VerilogParser#pullup_strength.
ctx
the parse tree
abstract def enterPulse_control_specparam(ctx: Pulse_control_specparamContext): Unit
Enter a parse tree produced by VerilogParser#pulse_control_specparam.
Enter a parse tree produced by VerilogParser#pulse_control_specparam.
ctx
the parse tree
abstract def enterPulsestyle_declaration(ctx: Pulsestyle_declarationContext): Unit
Enter a parse tree produced by VerilogParser#pulsestyle_declaration.
Enter a parse tree produced by VerilogParser#pulsestyle_declaration.
ctx
the parse tree
abstract def enterRange_(ctx: Range_Context): Unit
Enter a parse tree produced by VerilogParser#range_.
Enter a parse tree produced by VerilogParser#range_.
ctx
the parse tree
abstract def enterRange_expression(ctx: Range_expressionContext): Unit
Enter a parse tree produced by VerilogParser#range_expression.
Enter a parse tree produced by VerilogParser#range_expression.
ctx
the parse tree
abstract def enterRange_or_type(ctx: Range_or_typeContext): Unit
Enter a parse tree produced by VerilogParser#range_or_type.
Enter a parse tree produced by VerilogParser#range_or_type.
ctx
the parse tree
abstract def enterReal_declaration(ctx: Real_declarationContext): Unit
Enter a parse tree produced by VerilogParser#real_declaration.
Enter a parse tree produced by VerilogParser#real_declaration.
ctx
the parse tree
abstract def enterReal_identifier(ctx: Real_identifierContext): Unit
Enter a parse tree produced by VerilogParser#real_identifier.
Enter a parse tree produced by VerilogParser#real_identifier.
ctx
the parse tree
abstract def enterReal_type(ctx: Real_typeContext): Unit
Enter a parse tree produced by VerilogParser#real_type.
Enter a parse tree produced by VerilogParser#real_type.
ctx
the parse tree
abstract def enterRealtime_declaration(ctx: Realtime_declarationContext): Unit
Enter a parse tree produced by VerilogParser#realtime_declaration.
Enter a parse tree produced by VerilogParser#realtime_declaration.
ctx
the parse tree
abstract def enterReg_declaration(ctx: Reg_declarationContext): Unit
Enter a parse tree produced by VerilogParser#reg_declaration.
Enter a parse tree produced by VerilogParser#reg_declaration.
ctx
the parse tree
abstract def enterReject_limit_value(ctx: Reject_limit_valueContext): Unit
Enter a parse tree produced by VerilogParser#reject_limit_value.
Enter a parse tree produced by VerilogParser#reject_limit_value.
ctx
the parse tree
abstract def enterRemain_active_flag(ctx: Remain_active_flagContext): Unit
Enter a parse tree produced by VerilogParser#remain_active_flag.
Enter a parse tree produced by VerilogParser#remain_active_flag.
ctx
the parse tree
abstract def enterSeq_block(ctx: Seq_blockContext): Unit
Enter a parse tree produced by VerilogParser#seq_block.
Enter a parse tree produced by VerilogParser#seq_block.
ctx
the parse tree
abstract def enterShowcancelled_declaration(ctx: Showcancelled_declarationContext): Unit
Enter a parse tree produced by VerilogParser#showcancelled_declaration.
Enter a parse tree produced by VerilogParser#showcancelled_declaration.
ctx
the parse tree
abstract def enterSimple_arrayed_identifier(ctx: Simple_arrayed_identifierContext): Unit
Enter a parse tree produced by VerilogParser#simple_arrayed_identifier.
Enter a parse tree produced by VerilogParser#simple_arrayed_identifier.
ctx
the parse tree
abstract def enterSimple_hierarchical_branch(ctx: Simple_hierarchical_branchContext): Unit
Enter a parse tree produced by VerilogParser#simple_hierarchical_branch.
Enter a parse tree produced by VerilogParser#simple_hierarchical_branch.
ctx
the parse tree
abstract def enterSimple_hierarchical_identifier(ctx: Simple_hierarchical_identifierContext): Unit
Enter a parse tree produced by VerilogParser#simple_hierarchical_identifier.
Enter a parse tree produced by VerilogParser#simple_hierarchical_identifier.
ctx
the parse tree
abstract def enterSimple_path_declaration(ctx: Simple_path_declarationContext): Unit
Enter a parse tree produced by VerilogParser#simple_path_declaration.
Enter a parse tree produced by VerilogParser#simple_path_declaration.
ctx
the parse tree
abstract def enterSource_text(ctx: Source_textContext): Unit
Enter a parse tree produced by VerilogParser#source_text.
Enter a parse tree produced by VerilogParser#source_text.
ctx
the parse tree
abstract def enterSpecify_block(ctx: Specify_blockContext): Unit
Enter a parse tree produced by VerilogParser#specify_block.
Enter a parse tree produced by VerilogParser#specify_block.
ctx
the parse tree
abstract def enterSpecify_input_terminal_descriptor(ctx: Specify_input_terminal_descriptorContext): Unit
Enter a parse tree produced by VerilogParser#specify_input_terminal_descriptor.
Enter a parse tree produced by VerilogParser#specify_input_terminal_descriptor.
ctx
the parse tree
abstract def enterSpecify_item(ctx: Specify_itemContext): Unit
Enter a parse tree produced by VerilogParser#specify_item.
Enter a parse tree produced by VerilogParser#specify_item.
ctx
the parse tree
abstract def enterSpecify_output_terminal_descriptor(ctx: Specify_output_terminal_descriptorContext): Unit
Enter a parse tree produced by VerilogParser#specify_output_terminal_descriptor.
Enter a parse tree produced by VerilogParser#specify_output_terminal_descriptor.
ctx
the parse tree
abstract def enterSpecparam_assignment(ctx: Specparam_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#specparam_assignment.
Enter a parse tree produced by VerilogParser#specparam_assignment.
ctx
the parse tree
abstract def enterSpecparam_declaration(ctx: Specparam_declarationContext): Unit
Enter a parse tree produced by VerilogParser#specparam_declaration.
Enter a parse tree produced by VerilogParser#specparam_declaration.
ctx
the parse tree
abstract def enterSpecparam_identifier(ctx: Specparam_identifierContext): Unit
Enter a parse tree produced by VerilogParser#specparam_identifier.
Enter a parse tree produced by VerilogParser#specparam_identifier.
ctx
the parse tree
abstract def enterStamptime_condition(ctx: Stamptime_conditionContext): Unit
Enter a parse tree produced by VerilogParser#stamptime_condition.
Enter a parse tree produced by VerilogParser#stamptime_condition.
ctx
the parse tree
abstract def enterStart_edge_offset(ctx: Start_edge_offsetContext): Unit
Enter a parse tree produced by VerilogParser#start_edge_offset.
Enter a parse tree produced by VerilogParser#start_edge_offset.
ctx
the parse tree
abstract def enterState_dependent_path_declaration(ctx: State_dependent_path_declarationContext): Unit
Enter a parse tree produced by VerilogParser#state_dependent_path_declaration.
Enter a parse tree produced by VerilogParser#state_dependent_path_declaration.
ctx
the parse tree
abstract def enterStatement(ctx: StatementContext): Unit
Enter a parse tree produced by VerilogParser#statement.
Enter a parse tree produced by VerilogParser#statement.
ctx
the parse tree
abstract def enterStatement_or_null(ctx: Statement_or_nullContext): Unit
Enter a parse tree produced by VerilogParser#statement_or_null.
Enter a parse tree produced by VerilogParser#statement_or_null.
ctx
the parse tree
abstract def enterStrength0(ctx: Strength0Context): Unit
Enter a parse tree produced by VerilogParser#strength0.
Enter a parse tree produced by VerilogParser#strength0.
ctx
the parse tree
abstract def enterStrength1(ctx: Strength1Context): Unit
Enter a parse tree produced by VerilogParser#strength1.
Enter a parse tree produced by VerilogParser#strength1.
ctx
the parse tree
abstract def enterSystem_function_call(ctx: System_function_callContext): Unit
Enter a parse tree produced by VerilogParser#system_function_call.
Enter a parse tree produced by VerilogParser#system_function_call.
ctx
the parse tree
abstract def enterSystem_function_identifier(ctx: System_function_identifierContext): Unit
Enter a parse tree produced by VerilogParser#system_function_identifier.
Enter a parse tree produced by VerilogParser#system_function_identifier.
ctx
the parse tree
abstract def enterSystem_task_enable(ctx: System_task_enableContext): Unit
Enter a parse tree produced by VerilogParser#system_task_enable.
Enter a parse tree produced by VerilogParser#system_task_enable.
ctx
the parse tree
abstract def enterSystem_task_identifier(ctx: System_task_identifierContext): Unit
Enter a parse tree produced by VerilogParser#system_task_identifier.
Enter a parse tree produced by VerilogParser#system_task_identifier.
ctx
the parse tree
abstract def enterT01_path_delay_expression(ctx: T01_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#t01_path_delay_expression.
Enter a parse tree produced by VerilogParser#t01_path_delay_expression.
ctx
the parse tree
abstract def enterT0x_path_delay_expression(ctx: T0x_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#t0x_path_delay_expression.
Enter a parse tree produced by VerilogParser#t0x_path_delay_expression.
ctx
the parse tree
abstract def enterT0z_path_delay_expression(ctx: T0z_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#t0z_path_delay_expression.
Enter a parse tree produced by VerilogParser#t0z_path_delay_expression.
ctx
the parse tree
abstract def enterT10_path_delay_expression(ctx: T10_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#t10_path_delay_expression.
Enter a parse tree produced by VerilogParser#t10_path_delay_expression.
ctx
the parse tree
abstract def enterT1x_path_delay_expression(ctx: T1x_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#t1x_path_delay_expression.
Enter a parse tree produced by VerilogParser#t1x_path_delay_expression.
ctx
the parse tree
abstract def enterT1z_path_delay_expression(ctx: T1z_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#t1z_path_delay_expression.
Enter a parse tree produced by VerilogParser#t1z_path_delay_expression.
ctx
the parse tree
abstract def enterT_path_delay_expression(ctx: T_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#t_path_delay_expression.
Enter a parse tree produced by VerilogParser#t_path_delay_expression.
ctx
the parse tree
abstract def enterTask_declaration(ctx: Task_declarationContext): Unit
Enter a parse tree produced by VerilogParser#task_declaration.
Enter a parse tree produced by VerilogParser#task_declaration.
ctx
the parse tree
abstract def enterTask_enable(ctx: Task_enableContext): Unit
Enter a parse tree produced by VerilogParser#task_enable.
Enter a parse tree produced by VerilogParser#task_enable.
ctx
the parse tree
abstract def enterTask_identifier(ctx: Task_identifierContext): Unit
Enter a parse tree produced by VerilogParser#task_identifier.
Enter a parse tree produced by VerilogParser#task_identifier.
ctx
the parse tree
abstract def enterTask_item_declaration(ctx: Task_item_declarationContext): Unit
Enter a parse tree produced by VerilogParser#task_item_declaration.
Enter a parse tree produced by VerilogParser#task_item_declaration.
ctx
the parse tree
abstract def enterTask_port_item(ctx: Task_port_itemContext): Unit
Enter a parse tree produced by VerilogParser#task_port_item.
Enter a parse tree produced by VerilogParser#task_port_item.
ctx
the parse tree
abstract def enterTask_port_list(ctx: Task_port_listContext): Unit
Enter a parse tree produced by VerilogParser#task_port_list.
Enter a parse tree produced by VerilogParser#task_port_list.
ctx
the parse tree
abstract def enterTask_port_type(ctx: Task_port_typeContext): Unit
Enter a parse tree produced by VerilogParser#task_port_type.
Enter a parse tree produced by VerilogParser#task_port_type.
ctx
the parse tree
abstract def enterTerm(ctx: TermContext): Unit
Enter a parse tree produced by VerilogParser#term.
Enter a parse tree produced by VerilogParser#term.
ctx
the parse tree
abstract def enterTerminal_identifier(ctx: Terminal_identifierContext): Unit
Enter a parse tree produced by VerilogParser#terminal_identifier.
Enter a parse tree produced by VerilogParser#terminal_identifier.
ctx
the parse tree
abstract def enterText_macro_identifier(ctx: Text_macro_identifierContext): Unit
Enter a parse tree produced by VerilogParser#text_macro_identifier.
Enter a parse tree produced by VerilogParser#text_macro_identifier.
ctx
the parse tree
abstract def enterTf_decl_header(ctx: Tf_decl_headerContext): Unit
Enter a parse tree produced by VerilogParser#tf_decl_header.
Enter a parse tree produced by VerilogParser#tf_decl_header.
ctx
the parse tree
abstract def enterTf_declaration(ctx: Tf_declarationContext): Unit
Enter a parse tree produced by VerilogParser#tf_declaration.
Enter a parse tree produced by VerilogParser#tf_declaration.
ctx
the parse tree
abstract def enterTfall_path_delay_expression(ctx: Tfall_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#tfall_path_delay_expression.
Enter a parse tree produced by VerilogParser#tfall_path_delay_expression.
ctx
the parse tree
abstract def enterThreshold(ctx: ThresholdContext): Unit
Enter a parse tree produced by VerilogParser#threshold.
Enter a parse tree produced by VerilogParser#threshold.
ctx
the parse tree
abstract def enterTime_declaration(ctx: Time_declarationContext): Unit
Enter a parse tree produced by VerilogParser#time_declaration.
Enter a parse tree produced by VerilogParser#time_declaration.
ctx
the parse tree
abstract def enterTimescale_directive(ctx: Timescale_directiveContext): Unit
Enter a parse tree produced by VerilogParser#timescale_directive.
Enter a parse tree produced by VerilogParser#timescale_directive.
ctx
the parse tree
abstract def enterTiming_check_limit(ctx: Timing_check_limitContext): Unit
Enter a parse tree produced by VerilogParser#timing_check_limit.
Enter a parse tree produced by VerilogParser#timing_check_limit.
ctx
the parse tree
abstract def enterTopmodule_identifier(ctx: Topmodule_identifierContext): Unit
Enter a parse tree produced by VerilogParser#topmodule_identifier.
Enter a parse tree produced by VerilogParser#topmodule_identifier.
ctx
the parse tree
abstract def enterTrise_path_delay_expression(ctx: Trise_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#trise_path_delay_expression.
Enter a parse tree produced by VerilogParser#trise_path_delay_expression.
ctx
the parse tree
abstract def enterTx0_path_delay_expression(ctx: Tx0_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#tx0_path_delay_expression.
Enter a parse tree produced by VerilogParser#tx0_path_delay_expression.
ctx
the parse tree
abstract def enterTx1_path_delay_expression(ctx: Tx1_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#tx1_path_delay_expression.
Enter a parse tree produced by VerilogParser#tx1_path_delay_expression.
ctx
the parse tree
abstract def enterTxz_path_delay_expression(ctx: Txz_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#txz_path_delay_expression.
Enter a parse tree produced by VerilogParser#txz_path_delay_expression.
ctx
the parse tree
abstract def enterTz0_path_delay_expression(ctx: Tz0_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#tz0_path_delay_expression.
Enter a parse tree produced by VerilogParser#tz0_path_delay_expression.
ctx
the parse tree
abstract def enterTz1_path_delay_expression(ctx: Tz1_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#tz1_path_delay_expression.
Enter a parse tree produced by VerilogParser#tz1_path_delay_expression.
ctx
the parse tree
abstract def enterTz_path_delay_expression(ctx: Tz_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#tz_path_delay_expression.
Enter a parse tree produced by VerilogParser#tz_path_delay_expression.
ctx
the parse tree
abstract def enterTzx_path_delay_expression(ctx: Tzx_path_delay_expressionContext): Unit
Enter a parse tree produced by VerilogParser#tzx_path_delay_expression.
Enter a parse tree produced by VerilogParser#tzx_path_delay_expression.
ctx
the parse tree
abstract def enterUdp_identifier(ctx: Udp_identifierContext): Unit
Enter a parse tree produced by VerilogParser#udp_identifier.
Enter a parse tree produced by VerilogParser#udp_identifier.
ctx
the parse tree
abstract def enterUdp_instance_identifier(ctx: Udp_instance_identifierContext): Unit
Enter a parse tree produced by VerilogParser#udp_instance_identifier.
Enter a parse tree produced by VerilogParser#udp_instance_identifier.
ctx
the parse tree
abstract def enterUnary_module_path_operator(ctx: Unary_module_path_operatorContext): Unit
Enter a parse tree produced by VerilogParser#unary_module_path_operator.
Enter a parse tree produced by VerilogParser#unary_module_path_operator.
ctx
the parse tree
abstract def enterUnary_operator(ctx: Unary_operatorContext): Unit
Enter a parse tree produced by VerilogParser#unary_operator.
Enter a parse tree produced by VerilogParser#unary_operator.
ctx
the parse tree
abstract def enterUndef_directive(ctx: Undef_directiveContext): Unit
Enter a parse tree produced by VerilogParser#undef_directive.
Enter a parse tree produced by VerilogParser#undef_directive.
ctx
the parse tree
abstract def enterUse_clause(ctx: Use_clauseContext): Unit
Enter a parse tree produced by VerilogParser#use_clause.
Enter a parse tree produced by VerilogParser#use_clause.
ctx
the parse tree
abstract def enterUsing_defined_flag(ctx: Using_defined_flagContext): Unit
Enter a parse tree produced by VerilogParser#using_defined_flag.
Enter a parse tree produced by VerilogParser#using_defined_flag.
ctx
the parse tree
abstract def enterVariable_assignment(ctx: Variable_assignmentContext): Unit
Enter a parse tree produced by VerilogParser#variable_assignment.
Enter a parse tree produced by VerilogParser#variable_assignment.
ctx
the parse tree
abstract def enterVariable_concatenation(ctx: Variable_concatenationContext): Unit
Enter a parse tree produced by VerilogParser#variable_concatenation.
Enter a parse tree produced by VerilogParser#variable_concatenation.
ctx
the parse tree
abstract def enterVariable_concatenation_value(ctx: Variable_concatenation_valueContext): Unit
Enter a parse tree produced by VerilogParser#variable_concatenation_value.
Enter a parse tree produced by VerilogParser#variable_concatenation_value.
ctx
the parse tree
abstract def enterVariable_identifier(ctx: Variable_identifierContext): Unit
Enter a parse tree produced by VerilogParser#variable_identifier.
Enter a parse tree produced by VerilogParser#variable_identifier.
ctx
the parse tree
abstract def enterVariable_lvalue(ctx: Variable_lvalueContext): Unit
Enter a parse tree produced by VerilogParser#variable_lvalue.
Enter a parse tree produced by VerilogParser#variable_lvalue.
ctx
the parse tree
abstract def enterVariable_type(ctx: Variable_typeContext): Unit
Enter a parse tree produced by VerilogParser#variable_type.
Enter a parse tree produced by VerilogParser#variable_type.
ctx
the parse tree
abstract def enterWait_statement(ctx: Wait_statementContext): Unit
Enter a parse tree produced by VerilogParser#wait_statement.
Enter a parse tree produced by VerilogParser#wait_statement.
ctx
the parse tree
abstract def enterWidth_constant_expression(ctx: Width_constant_expressionContext): Unit
Enter a parse tree produced by VerilogParser#width_constant_expression.
Enter a parse tree produced by VerilogParser#width_constant_expression.
ctx
the parse tree
abstract def exitAlways_construct(ctx: Always_constructContext): Unit
Exit a parse tree produced by VerilogParser#always_construct.
Exit a parse tree produced by VerilogParser#always_construct.
ctx
the parse tree
abstract def exitArrayed_identifier(ctx: Arrayed_identifierContext): Unit
Exit a parse tree produced by VerilogParser#arrayed_identifier.
Exit a parse tree produced by VerilogParser#arrayed_identifier.
ctx
the parse tree
abstract def exitAttr_name(ctx: Attr_nameContext): Unit
Exit a parse tree produced by VerilogParser#attr_name.
Exit a parse tree produced by VerilogParser#attr_name.
ctx
the parse tree
abstract def exitAttr_spec(ctx: Attr_specContext): Unit
Exit a parse tree produced by VerilogParser#attr_spec.
Exit a parse tree produced by VerilogParser#attr_spec.
ctx
the parse tree
abstract def exitAttribute_instance(ctx: Attribute_instanceContext): Unit
Exit a parse tree produced by VerilogParser#attribute_instance.
Exit a parse tree produced by VerilogParser#attribute_instance.
ctx
the parse tree
abstract def exitBase_expression(ctx: Base_expressionContext): Unit
Exit a parse tree produced by VerilogParser#base_expression.
Exit a parse tree produced by VerilogParser#base_expression.
ctx
the parse tree
abstract def exitBinary_module_path_operator(ctx: Binary_module_path_operatorContext): Unit
Exit a parse tree produced by VerilogParser#binary_module_path_operator.
Exit a parse tree produced by VerilogParser#binary_module_path_operator.
ctx
the parse tree
abstract def exitBinary_operator(ctx: Binary_operatorContext): Unit
Exit a parse tree produced by VerilogParser#binary_operator.
Exit a parse tree produced by VerilogParser#binary_operator.
ctx
the parse tree
abstract def exitBinary_operator_or(ctx: Binary_operator_orContext): Unit
Exit a parse tree produced by VerilogParser#binary_operator_or.
Exit a parse tree produced by VerilogParser#binary_operator_or.
ctx
the parse tree
abstract def exitBlock_identifier(ctx: Block_identifierContext): Unit
Exit a parse tree produced by VerilogParser#block_identifier.
Exit a parse tree produced by VerilogParser#block_identifier.
ctx
the parse tree
abstract def exitBlock_item_declaration(ctx: Block_item_declarationContext): Unit
Exit a parse tree produced by VerilogParser#block_item_declaration.
Exit a parse tree produced by VerilogParser#block_item_declaration.
ctx
the parse tree
abstract def exitBlock_reg_declaration(ctx: Block_reg_declarationContext): Unit
Exit a parse tree produced by VerilogParser#block_reg_declaration.
Exit a parse tree produced by VerilogParser#block_reg_declaration.
ctx
the parse tree
abstract def exitBlock_variable_type(ctx: Block_variable_typeContext): Unit
Exit a parse tree produced by VerilogParser#block_variable_type.
Exit a parse tree produced by VerilogParser#block_variable_type.
ctx
the parse tree
abstract def exitBlocking_assignment(ctx: Blocking_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#blocking_assignment.
Exit a parse tree produced by VerilogParser#blocking_assignment.
ctx
the parse tree
abstract def exitCase_body(ctx: Case_bodyContext): Unit
Exit a parse tree produced by VerilogParser#case_body.
Exit a parse tree produced by VerilogParser#case_body.
ctx
the parse tree
abstract def exitCase_default_item(ctx: Case_default_itemContext): Unit
Exit a parse tree produced by VerilogParser#case_default_item.
Exit a parse tree produced by VerilogParser#case_default_item.
ctx
the parse tree
abstract def exitCase_item(ctx: Case_itemContext): Unit
Exit a parse tree produced by VerilogParser#case_item.
Exit a parse tree produced by VerilogParser#case_item.
ctx
the parse tree
abstract def exitCase_statement(ctx: Case_statementContext): Unit
Exit a parse tree produced by VerilogParser#case_statement.
Exit a parse tree produced by VerilogParser#case_statement.
ctx
the parse tree
abstract def exitCell_clause(ctx: Cell_clauseContext): Unit
Exit a parse tree produced by VerilogParser#cell_clause.
Exit a parse tree produced by VerilogParser#cell_clause.
ctx
the parse tree
abstract def exitCell_identifier(ctx: Cell_identifierContext): Unit
Exit a parse tree produced by VerilogParser#cell_identifier.
Exit a parse tree produced by VerilogParser#cell_identifier.
ctx
the parse tree
abstract def exitCharge_strength(ctx: Charge_strengthContext): Unit
Exit a parse tree produced by VerilogParser#charge_strength.
Exit a parse tree produced by VerilogParser#charge_strength.
ctx
the parse tree
abstract def exitChecktime_condition(ctx: Checktime_conditionContext): Unit
Exit a parse tree produced by VerilogParser#checktime_condition.
Exit a parse tree produced by VerilogParser#checktime_condition.
ctx
the parse tree
abstract def exitCmos_switch_instance(ctx: Cmos_switch_instanceContext): Unit
Exit a parse tree produced by VerilogParser#cmos_switch_instance.
Exit a parse tree produced by VerilogParser#cmos_switch_instance.
ctx
the parse tree
abstract def exitCmos_switchtype(ctx: Cmos_switchtypeContext): Unit
Exit a parse tree produced by VerilogParser#cmos_switchtype.
Exit a parse tree produced by VerilogParser#cmos_switchtype.
ctx
the parse tree
abstract def exitConcatenation(ctx: ConcatenationContext): Unit
Exit a parse tree produced by VerilogParser#concatenation.
Exit a parse tree produced by VerilogParser#concatenation.
ctx
the parse tree
abstract def exitConditional_statement(ctx: Conditional_statementContext): Unit
Exit a parse tree produced by VerilogParser#conditional_statement.
Exit a parse tree produced by VerilogParser#conditional_statement.
ctx
the parse tree
abstract def exitConditional_statement_body(ctx: Conditional_statement_bodyContext): Unit
Exit a parse tree produced by VerilogParser#conditional_statement_body.
Exit a parse tree produced by VerilogParser#conditional_statement_body.
ctx
the parse tree
abstract def exitConditional_statement_chain(ctx: Conditional_statement_chainContext): Unit
Exit a parse tree produced by VerilogParser#conditional_statement_chain.
Exit a parse tree produced by VerilogParser#conditional_statement_chain.
ctx
the parse tree
abstract def exitConditional_statement_else_chain(ctx: Conditional_statement_else_chainContext): Unit
Exit a parse tree produced by VerilogParser#conditional_statement_else_chain.
Exit a parse tree produced by VerilogParser#conditional_statement_else_chain.
ctx
the parse tree
abstract def exitConditional_statement_else_tail(ctx: Conditional_statement_else_tailContext): Unit
Exit a parse tree produced by VerilogParser#conditional_statement_else_tail.
Exit a parse tree produced by VerilogParser#conditional_statement_else_tail.
ctx
the parse tree
abstract def exitConditional_statement_head(ctx: Conditional_statement_headContext): Unit
Exit a parse tree produced by VerilogParser#conditional_statement_head.
Exit a parse tree produced by VerilogParser#conditional_statement_head.
ctx
the parse tree
abstract def exitConfig_declaration(ctx: Config_declarationContext): Unit
Exit a parse tree produced by VerilogParser#config_declaration.
Exit a parse tree produced by VerilogParser#config_declaration.
ctx
the parse tree
abstract def exitConfig_identifier(ctx: Config_identifierContext): Unit
Exit a parse tree produced by VerilogParser#config_identifier.
Exit a parse tree produced by VerilogParser#config_identifier.
ctx
the parse tree
abstract def exitConfig_rule_statement(ctx: Config_rule_statementContext): Unit
Exit a parse tree produced by VerilogParser#config_rule_statement.
Exit a parse tree produced by VerilogParser#config_rule_statement.
ctx
the parse tree
abstract def exitConstant_base_expression(ctx: Constant_base_expressionContext): Unit
Exit a parse tree produced by VerilogParser#constant_base_expression.
Exit a parse tree produced by VerilogParser#constant_base_expression.
ctx
the parse tree
abstract def exitConstant_concatenation(ctx: Constant_concatenationContext): Unit
Exit a parse tree produced by VerilogParser#constant_concatenation.
Exit a parse tree produced by VerilogParser#constant_concatenation.
ctx
the parse tree
abstract def exitConstant_expression(ctx: Constant_expressionContext): Unit
Exit a parse tree produced by VerilogParser#constant_expression.
Exit a parse tree produced by VerilogParser#constant_expression.
ctx
the parse tree
abstract def exitConstant_function_call(ctx: Constant_function_callContext): Unit
Exit a parse tree produced by VerilogParser#constant_function_call.
Exit a parse tree produced by VerilogParser#constant_function_call.
ctx
the parse tree
abstract def exitConstant_mintypmax_expression(ctx: Constant_mintypmax_expressionContext): Unit
Exit a parse tree produced by VerilogParser#constant_mintypmax_expression.
Exit a parse tree produced by VerilogParser#constant_mintypmax_expression.
ctx
the parse tree
abstract def exitConstant_multiple_concatenation(ctx: Constant_multiple_concatenationContext): Unit
Exit a parse tree produced by VerilogParser#constant_multiple_concatenation.
Exit a parse tree produced by VerilogParser#constant_multiple_concatenation.
ctx
the parse tree
abstract def exitConstant_primary(ctx: Constant_primaryContext): Unit
Exit a parse tree produced by VerilogParser#constant_primary.
Exit a parse tree produced by VerilogParser#constant_primary.
ctx
the parse tree
abstract def exitConstant_range_expression(ctx: Constant_range_expressionContext): Unit
Exit a parse tree produced by VerilogParser#constant_range_expression.
Exit a parse tree produced by VerilogParser#constant_range_expression.
ctx
the parse tree
abstract def exitContinuous_assign(ctx: Continuous_assignContext): Unit
Exit a parse tree produced by VerilogParser#continuous_assign.
Exit a parse tree produced by VerilogParser#continuous_assign.
ctx
the parse tree
abstract def exitCreate_defined_flag(ctx: Create_defined_flagContext): Unit
Exit a parse tree produced by VerilogParser#create_defined_flag.
Exit a parse tree produced by VerilogParser#create_defined_flag.
ctx
the parse tree
abstract def exitCreate_defined_term(ctx: Create_defined_termContext): Unit
Exit a parse tree produced by VerilogParser#create_defined_term.
Exit a parse tree produced by VerilogParser#create_defined_term.
ctx
the parse tree
abstract def exitData_source_expression(ctx: Data_source_expressionContext): Unit
Exit a parse tree produced by VerilogParser#data_source_expression.
Exit a parse tree produced by VerilogParser#data_source_expression.
ctx
the parse tree
abstract def exitDefault_clause(ctx: Default_clauseContext): Unit
Exit a parse tree produced by VerilogParser#default_clause.
Exit a parse tree produced by VerilogParser#default_clause.
ctx
the parse tree
abstract def exitDefault_nettype_directive(ctx: Default_nettype_directiveContext): Unit
Exit a parse tree produced by VerilogParser#default_nettype_directive.
Exit a parse tree produced by VerilogParser#default_nettype_directive.
ctx
the parse tree
abstract def exitDefine_directive(ctx: Define_directiveContext): Unit
Exit a parse tree produced by VerilogParser#define_directive.
Exit a parse tree produced by VerilogParser#define_directive.
ctx
the parse tree
abstract def exitDefined_flag(ctx: Defined_flagContext): Unit
Exit a parse tree produced by VerilogParser#defined_flag.
Exit a parse tree produced by VerilogParser#defined_flag.
ctx
the parse tree
abstract def exitDelay2(ctx: Delay2Context): Unit
Exit a parse tree produced by VerilogParser#delay2.
Exit a parse tree produced by VerilogParser#delay2.
ctx
the parse tree
abstract def exitDelay3(ctx: Delay3Context): Unit
Exit a parse tree produced by VerilogParser#delay3.
Exit a parse tree produced by VerilogParser#delay3.
ctx
the parse tree
abstract def exitDelay_control(ctx: Delay_controlContext): Unit
Exit a parse tree produced by VerilogParser#delay_control.
Exit a parse tree produced by VerilogParser#delay_control.
ctx
the parse tree
abstract def exitDelay_or_event_control(ctx: Delay_or_event_controlContext): Unit
Exit a parse tree produced by VerilogParser#delay_or_event_control.
Exit a parse tree produced by VerilogParser#delay_or_event_control.
ctx
the parse tree
abstract def exitDelay_value(ctx: Delay_valueContext): Unit
Exit a parse tree produced by VerilogParser#delay_value.
Exit a parse tree produced by VerilogParser#delay_value.
ctx
the parse tree
abstract def exitDelayed_data(ctx: Delayed_dataContext): Unit
Exit a parse tree produced by VerilogParser#delayed_data.
Exit a parse tree produced by VerilogParser#delayed_data.
ctx
the parse tree
abstract def exitDelayed_reference(ctx: Delayed_referenceContext): Unit
Exit a parse tree produced by VerilogParser#delayed_reference.
Exit a parse tree produced by VerilogParser#delayed_reference.
ctx
the parse tree
abstract def exitDescription(ctx: DescriptionContext): Unit
Exit a parse tree produced by VerilogParser#description.
Exit a parse tree produced by VerilogParser#description.
ctx
the parse tree
abstract def exitDesign_statement(ctx: Design_statementContext): Unit
Exit a parse tree produced by VerilogParser#design_statement.
Exit a parse tree produced by VerilogParser#design_statement.
ctx
the parse tree
abstract def exitDimension(ctx: DimensionContext): Unit
Exit a parse tree produced by VerilogParser#dimension.
Exit a parse tree produced by VerilogParser#dimension.
ctx
the parse tree
abstract def exitDimension_constant_expression(ctx: Dimension_constant_expressionContext): Unit
Exit a parse tree produced by VerilogParser#dimension_constant_expression.
Exit a parse tree produced by VerilogParser#dimension_constant_expression.
ctx
the parse tree
abstract def exitDirective(ctx: DirectiveContext): Unit
Exit a parse tree produced by VerilogParser#directive.
Exit a parse tree produced by VerilogParser#directive.
ctx
the parse tree
abstract def exitDisable_statement(ctx: Disable_statementContext): Unit
Exit a parse tree produced by VerilogParser#disable_statement.
Exit a parse tree produced by VerilogParser#disable_statement.
ctx
the parse tree
abstract def exitDrive_strength(ctx: Drive_strengthContext): Unit
Exit a parse tree produced by VerilogParser#drive_strength.
Exit a parse tree produced by VerilogParser#drive_strength.
ctx
the parse tree
abstract def exitEdge_identifier(ctx: Edge_identifierContext): Unit
Exit a parse tree produced by VerilogParser#edge_identifier.
Exit a parse tree produced by VerilogParser#edge_identifier.
ctx
the parse tree
abstract def exitEdge_sensitive_path_declaration(ctx: Edge_sensitive_path_declarationContext): Unit
Exit a parse tree produced by VerilogParser#edge_sensitive_path_declaration.
Exit a parse tree produced by VerilogParser#edge_sensitive_path_declaration.
ctx
the parse tree
abstract def exitElse_directive(ctx: Else_directiveContext): Unit
Exit a parse tree produced by VerilogParser#else_directive.
Exit a parse tree produced by VerilogParser#else_directive.
ctx
the parse tree
abstract def exitElsif_directive(ctx: Elsif_directiveContext): Unit
Exit a parse tree produced by VerilogParser#elsif_directive.
Exit a parse tree produced by VerilogParser#elsif_directive.
ctx
the parse tree
abstract def exitEnable_gate_instance(ctx: Enable_gate_instanceContext): Unit
Exit a parse tree produced by VerilogParser#enable_gate_instance.
Exit a parse tree produced by VerilogParser#enable_gate_instance.
ctx
the parse tree
abstract def exitEnable_gatetype(ctx: Enable_gatetypeContext): Unit
Exit a parse tree produced by VerilogParser#enable_gatetype.
Exit a parse tree produced by VerilogParser#enable_gatetype.
ctx
the parse tree
abstract def exitEnable_terminal(ctx: Enable_terminalContext): Unit
Exit a parse tree produced by VerilogParser#enable_terminal.
Exit a parse tree produced by VerilogParser#enable_terminal.
ctx
the parse tree
abstract def exitEnd_edge_offset(ctx: End_edge_offsetContext): Unit
Exit a parse tree produced by VerilogParser#end_edge_offset.
Exit a parse tree produced by VerilogParser#end_edge_offset.
ctx
the parse tree
abstract def exitEndif_directive(ctx: Endif_directiveContext): Unit
Exit a parse tree produced by VerilogParser#endif_directive.
Exit a parse tree produced by VerilogParser#endif_directive.
ctx
the parse tree
abstract def exitError_limit_value(ctx: Error_limit_valueContext): Unit
Exit a parse tree produced by VerilogParser#error_limit_value.
Exit a parse tree produced by VerilogParser#error_limit_value.
ctx
the parse tree
abstract def exitEscaped_arrayed_identifier(ctx: Escaped_arrayed_identifierContext): Unit
Exit a parse tree produced by VerilogParser#escaped_arrayed_identifier.
Exit a parse tree produced by VerilogParser#escaped_arrayed_identifier.
ctx
the parse tree
abstract def exitEscaped_hierarchical_branch(ctx: Escaped_hierarchical_branchContext): Unit
Exit a parse tree produced by VerilogParser#escaped_hierarchical_branch.
Exit a parse tree produced by VerilogParser#escaped_hierarchical_branch.
ctx
the parse tree
abstract def exitEscaped_hierarchical_identifier(ctx: Escaped_hierarchical_identifierContext): Unit
Exit a parse tree produced by VerilogParser#escaped_hierarchical_identifier.
Exit a parse tree produced by VerilogParser#escaped_hierarchical_identifier.
ctx
the parse tree
abstract def exitEvent_based_flag(ctx: Event_based_flagContext): Unit
Exit a parse tree produced by VerilogParser#event_based_flag.
Exit a parse tree produced by VerilogParser#event_based_flag.
ctx
the parse tree
abstract def exitEvent_control(ctx: Event_controlContext): Unit
Exit a parse tree produced by VerilogParser#event_control.
Exit a parse tree produced by VerilogParser#event_control.
ctx
the parse tree
abstract def exitEvent_declaration(ctx: Event_declarationContext): Unit
Exit a parse tree produced by VerilogParser#event_declaration.
Exit a parse tree produced by VerilogParser#event_declaration.
ctx
the parse tree
abstract def exitEvent_expression(ctx: Event_expressionContext): Unit
Exit a parse tree produced by VerilogParser#event_expression.
Exit a parse tree produced by VerilogParser#event_expression.
ctx
the parse tree
abstract def exitEvent_identifier(ctx: Event_identifierContext): Unit
Exit a parse tree produced by VerilogParser#event_identifier.
Exit a parse tree produced by VerilogParser#event_identifier.
ctx
the parse tree
abstract def exitEvent_primary(ctx: Event_primaryContext): Unit
Exit a parse tree produced by VerilogParser#event_primary.
Exit a parse tree produced by VerilogParser#event_primary.
ctx
the parse tree
abstract def exitEvent_trigger(ctx: Event_triggerContext): Unit
Exit a parse tree produced by VerilogParser#event_trigger.
Exit a parse tree produced by VerilogParser#event_trigger.
ctx
the parse tree
abstract def exitEveryRule(arg0: ParserRuleContext): Unit
Definition Classes
ParseTreeListener
abstract def exitExpression(ctx: ExpressionContext): Unit
Exit a parse tree produced by VerilogParser#expression.
Exit a parse tree produced by VerilogParser#expression.
ctx
the parse tree
abstract def exitFull_edge_sensitive_path_description(ctx: Full_edge_sensitive_path_descriptionContext): Unit
Exit a parse tree produced by VerilogParser#full_edge_sensitive_path_description.
Exit a parse tree produced by VerilogParser#full_edge_sensitive_path_description.
ctx
the parse tree
abstract def exitFull_path_description(ctx: Full_path_descriptionContext): Unit
Exit a parse tree produced by VerilogParser#full_path_description.
Exit a parse tree produced by VerilogParser#full_path_description.
ctx
the parse tree
abstract def exitFunction_blocking_assignment(ctx: Function_blocking_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#function_blocking_assignment.
Exit a parse tree produced by VerilogParser#function_blocking_assignment.
ctx
the parse tree
abstract def exitFunction_call(ctx: Function_callContext): Unit
Exit a parse tree produced by VerilogParser#function_call.
Exit a parse tree produced by VerilogParser#function_call.
ctx
the parse tree
abstract def exitFunction_case_body(ctx: Function_case_bodyContext): Unit
Exit a parse tree produced by VerilogParser#function_case_body.
Exit a parse tree produced by VerilogParser#function_case_body.
ctx
the parse tree
abstract def exitFunction_case_item(ctx: Function_case_itemContext): Unit
Exit a parse tree produced by VerilogParser#function_case_item.
Exit a parse tree produced by VerilogParser#function_case_item.
ctx
the parse tree
abstract def exitFunction_case_statement(ctx: Function_case_statementContext): Unit
Exit a parse tree produced by VerilogParser#function_case_statement.
Exit a parse tree produced by VerilogParser#function_case_statement.
ctx
the parse tree
abstract def exitFunction_conditional_statement(ctx: Function_conditional_statementContext): Unit
Exit a parse tree produced by VerilogParser#function_conditional_statement.
Exit a parse tree produced by VerilogParser#function_conditional_statement.
ctx
the parse tree
abstract def exitFunction_declaration(ctx: Function_declarationContext): Unit
Exit a parse tree produced by VerilogParser#function_declaration.
Exit a parse tree produced by VerilogParser#function_declaration.
ctx
the parse tree
abstract def exitFunction_identifier(ctx: Function_identifierContext): Unit
Exit a parse tree produced by VerilogParser#function_identifier.
Exit a parse tree produced by VerilogParser#function_identifier.
ctx
the parse tree
abstract def exitFunction_if_else_if_statement(ctx: Function_if_else_if_statementContext): Unit
Exit a parse tree produced by VerilogParser#function_if_else_if_statement.
Exit a parse tree produced by VerilogParser#function_if_else_if_statement.
ctx
the parse tree
abstract def exitFunction_item_declaration(ctx: Function_item_declarationContext): Unit
Exit a parse tree produced by VerilogParser#function_item_declaration.
Exit a parse tree produced by VerilogParser#function_item_declaration.
ctx
the parse tree
abstract def exitFunction_loop_statement(ctx: Function_loop_statementContext): Unit
Exit a parse tree produced by VerilogParser#function_loop_statement.
Exit a parse tree produced by VerilogParser#function_loop_statement.
ctx
the parse tree
abstract def exitFunction_port(ctx: Function_portContext): Unit
Exit a parse tree produced by VerilogParser#function_port.
Exit a parse tree produced by VerilogParser#function_port.
ctx
the parse tree
abstract def exitFunction_port_list(ctx: Function_port_listContext): Unit
Exit a parse tree produced by VerilogParser#function_port_list.
Exit a parse tree produced by VerilogParser#function_port_list.
ctx
the parse tree
abstract def exitFunction_seq_block(ctx: Function_seq_blockContext): Unit
Exit a parse tree produced by VerilogParser#function_seq_block.
Exit a parse tree produced by VerilogParser#function_seq_block.
ctx
the parse tree
abstract def exitFunction_statement(ctx: Function_statementContext): Unit
Exit a parse tree produced by VerilogParser#function_statement.
Exit a parse tree produced by VerilogParser#function_statement.
ctx
the parse tree
abstract def exitFunction_statement_or_null(ctx: Function_statement_or_nullContext): Unit
Exit a parse tree produced by VerilogParser#function_statement_or_null.
Exit a parse tree produced by VerilogParser#function_statement_or_null.
ctx
the parse tree
abstract def exitGate_instance_identifier(ctx: Gate_instance_identifierContext): Unit
Exit a parse tree produced by VerilogParser#gate_instance_identifier.
Exit a parse tree produced by VerilogParser#gate_instance_identifier.
ctx
the parse tree
abstract def exitGate_instantiation(ctx: Gate_instantiationContext): Unit
Exit a parse tree produced by VerilogParser#gate_instantiation.
Exit a parse tree produced by VerilogParser#gate_instantiation.
ctx
the parse tree
abstract def exitGenerate_block(ctx: Generate_blockContext): Unit
Exit a parse tree produced by VerilogParser#generate_block.
Exit a parse tree produced by VerilogParser#generate_block.
ctx
the parse tree
abstract def exitGenerate_block_identifier(ctx: Generate_block_identifierContext): Unit
Exit a parse tree produced by VerilogParser#generate_block_identifier.
Exit a parse tree produced by VerilogParser#generate_block_identifier.
ctx
the parse tree
abstract def exitGenerate_case_body(ctx: Generate_case_bodyContext): Unit
Exit a parse tree produced by VerilogParser#generate_case_body.
Exit a parse tree produced by VerilogParser#generate_case_body.
ctx
the parse tree
abstract def exitGenerate_case_statement(ctx: Generate_case_statementContext): Unit
Exit a parse tree produced by VerilogParser#generate_case_statement.
Exit a parse tree produced by VerilogParser#generate_case_statement.
ctx
the parse tree
abstract def exitGenerate_conditional_statement(ctx: Generate_conditional_statementContext): Unit
Exit a parse tree produced by VerilogParser#generate_conditional_statement.
Exit a parse tree produced by VerilogParser#generate_conditional_statement.
ctx
the parse tree
abstract def exitGenerate_item(ctx: Generate_itemContext): Unit
Exit a parse tree produced by VerilogParser#generate_item.
Exit a parse tree produced by VerilogParser#generate_item.
ctx
the parse tree
abstract def exitGenerate_item_or_null(ctx: Generate_item_or_nullContext): Unit
Exit a parse tree produced by VerilogParser#generate_item_or_null.
Exit a parse tree produced by VerilogParser#generate_item_or_null.
ctx
the parse tree
abstract def exitGenerate_loop_statement(ctx: Generate_loop_statementContext): Unit
Exit a parse tree produced by VerilogParser#generate_loop_statement.
Exit a parse tree produced by VerilogParser#generate_loop_statement.
ctx
the parse tree
abstract def exitGenerated_instantiation(ctx: Generated_instantiationContext): Unit
Exit a parse tree produced by VerilogParser#generated_instantiation.
Exit a parse tree produced by VerilogParser#generated_instantiation.
ctx
the parse tree
abstract def exitGenvar_assignment(ctx: Genvar_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#genvar_assignment.
Exit a parse tree produced by VerilogParser#genvar_assignment.
ctx
the parse tree
abstract def exitGenvar_case_item(ctx: Genvar_case_itemContext): Unit
Exit a parse tree produced by VerilogParser#genvar_case_item.
Exit a parse tree produced by VerilogParser#genvar_case_item.
ctx
the parse tree
abstract def exitGenvar_declaration(ctx: Genvar_declarationContext): Unit
Exit a parse tree produced by VerilogParser#genvar_declaration.
Exit a parse tree produced by VerilogParser#genvar_declaration.
ctx
the parse tree
abstract def exitGenvar_function_call(ctx: Genvar_function_callContext): Unit
Exit a parse tree produced by VerilogParser#genvar_function_call.
Exit a parse tree produced by VerilogParser#genvar_function_call.
ctx
the parse tree
abstract def exitGenvar_function_identifier(ctx: Genvar_function_identifierContext): Unit
Exit a parse tree produced by VerilogParser#genvar_function_identifier.
Exit a parse tree produced by VerilogParser#genvar_function_identifier.
ctx
the parse tree
abstract def exitGenvar_identifier(ctx: Genvar_identifierContext): Unit
Exit a parse tree produced by VerilogParser#genvar_identifier.
Exit a parse tree produced by VerilogParser#genvar_identifier.
ctx
the parse tree
abstract def exitHierarchical_block_identifier(ctx: Hierarchical_block_identifierContext): Unit
Exit a parse tree produced by VerilogParser#hierarchical_block_identifier.
Exit a parse tree produced by VerilogParser#hierarchical_block_identifier.
ctx
the parse tree
abstract def exitHierarchical_event_identifier(ctx: Hierarchical_event_identifierContext): Unit
Exit a parse tree produced by VerilogParser#hierarchical_event_identifier.
Exit a parse tree produced by VerilogParser#hierarchical_event_identifier.
ctx
the parse tree
abstract def exitHierarchical_function_identifier(ctx: Hierarchical_function_identifierContext): Unit
Exit a parse tree produced by VerilogParser#hierarchical_function_identifier.
Exit a parse tree produced by VerilogParser#hierarchical_function_identifier.
ctx
the parse tree
abstract def exitHierarchical_identifier(ctx: Hierarchical_identifierContext): Unit
Exit a parse tree produced by VerilogParser#hierarchical_identifier.
Exit a parse tree produced by VerilogParser#hierarchical_identifier.
ctx
the parse tree
abstract def exitHierarchical_net_identifier(ctx: Hierarchical_net_identifierContext): Unit
Exit a parse tree produced by VerilogParser#hierarchical_net_identifier.
Exit a parse tree produced by VerilogParser#hierarchical_net_identifier.
ctx
the parse tree
abstract def exitHierarchical_task_identifier(ctx: Hierarchical_task_identifierContext): Unit
Exit a parse tree produced by VerilogParser#hierarchical_task_identifier.
Exit a parse tree produced by VerilogParser#hierarchical_task_identifier.
ctx
the parse tree
abstract def exitHierarchical_variable_identifier(ctx: Hierarchical_variable_identifierContext): Unit
Exit a parse tree produced by VerilogParser#hierarchical_variable_identifier.
Exit a parse tree produced by VerilogParser#hierarchical_variable_identifier.
ctx
the parse tree
abstract def exitIdentifier(ctx: IdentifierContext): Unit
Exit a parse tree produced by VerilogParser#identifier.
Exit a parse tree produced by VerilogParser#identifier.
ctx
the parse tree
abstract def exitIfdef_directive(ctx: Ifdef_directiveContext): Unit
Exit a parse tree produced by VerilogParser#ifdef_directive.
Exit a parse tree produced by VerilogParser#ifdef_directive.
ctx
the parse tree
abstract def exitIfndef_directive(ctx: Ifndef_directiveContext): Unit
Exit a parse tree produced by VerilogParser#ifndef_directive.
Exit a parse tree produced by VerilogParser#ifndef_directive.
ctx
the parse tree
abstract def exitInclude_directive(ctx: Include_directiveContext): Unit
Exit a parse tree produced by VerilogParser#include_directive.
Exit a parse tree produced by VerilogParser#include_directive.
ctx
the parse tree
abstract def exitIncomplete_condition_statement(ctx: Incomplete_condition_statementContext): Unit
Exit a parse tree produced by VerilogParser#incomplete_condition_statement.
Exit a parse tree produced by VerilogParser#incomplete_condition_statement.
ctx
the parse tree
abstract def exitIncomplete_statement(ctx: Incomplete_statementContext): Unit
Exit a parse tree produced by VerilogParser#incomplete_statement.
Exit a parse tree produced by VerilogParser#incomplete_statement.
ctx
the parse tree
abstract def exitInitial_construct(ctx: Initial_constructContext): Unit
Exit a parse tree produced by VerilogParser#initial_construct.
Exit a parse tree produced by VerilogParser#initial_construct.
ctx
the parse tree
abstract def exitInout_declaration(ctx: Inout_declarationContext): Unit
Exit a parse tree produced by VerilogParser#inout_declaration.
Exit a parse tree produced by VerilogParser#inout_declaration.
ctx
the parse tree
abstract def exitInout_port_identifier(ctx: Inout_port_identifierContext): Unit
Exit a parse tree produced by VerilogParser#inout_port_identifier.
Exit a parse tree produced by VerilogParser#inout_port_identifier.
ctx
the parse tree
abstract def exitInout_terminal(ctx: Inout_terminalContext): Unit
Exit a parse tree produced by VerilogParser#inout_terminal.
Exit a parse tree produced by VerilogParser#inout_terminal.
ctx
the parse tree
abstract def exitInput_declaration(ctx: Input_declarationContext): Unit
Exit a parse tree produced by VerilogParser#input_declaration.
Exit a parse tree produced by VerilogParser#input_declaration.
ctx
the parse tree
abstract def exitInput_identifier(ctx: Input_identifierContext): Unit
Exit a parse tree produced by VerilogParser#input_identifier.
Exit a parse tree produced by VerilogParser#input_identifier.
ctx
the parse tree
abstract def exitInput_port_identifier(ctx: Input_port_identifierContext): Unit
Exit a parse tree produced by VerilogParser#input_port_identifier.
Exit a parse tree produced by VerilogParser#input_port_identifier.
ctx
the parse tree
abstract def exitInput_terminal(ctx: Input_terminalContext): Unit
Exit a parse tree produced by VerilogParser#input_terminal.
Exit a parse tree produced by VerilogParser#input_terminal.
ctx
the parse tree
abstract def exitInst_clause(ctx: Inst_clauseContext): Unit
Exit a parse tree produced by VerilogParser#inst_clause.
Exit a parse tree produced by VerilogParser#inst_clause.
ctx
the parse tree
abstract def exitInst_name(ctx: Inst_nameContext): Unit
Exit a parse tree produced by VerilogParser#inst_name.
Exit a parse tree produced by VerilogParser#inst_name.
ctx
the parse tree
abstract def exitInstance_identifier(ctx: Instance_identifierContext): Unit
Exit a parse tree produced by VerilogParser#instance_identifier.
Exit a parse tree produced by VerilogParser#instance_identifier.
ctx
the parse tree
abstract def exitInteger_declaration(ctx: Integer_declarationContext): Unit
Exit a parse tree produced by VerilogParser#integer_declaration.
Exit a parse tree produced by VerilogParser#integer_declaration.
ctx
the parse tree
abstract def exitLiblist_clause(ctx: Liblist_clauseContext): Unit
Exit a parse tree produced by VerilogParser#liblist_clause.
Exit a parse tree produced by VerilogParser#liblist_clause.
ctx
the parse tree
abstract def exitLibrary_identifier(ctx: Library_identifierContext): Unit
Exit a parse tree produced by VerilogParser#library_identifier.
Exit a parse tree produced by VerilogParser#library_identifier.
ctx
the parse tree
abstract def exitLimit_value(ctx: Limit_valueContext): Unit
Exit a parse tree produced by VerilogParser#limit_value.
Exit a parse tree produced by VerilogParser#limit_value.
ctx
the parse tree
abstract def exitList_of_block_variable_identifiers(ctx: List_of_block_variable_identifiersContext): Unit
Exit a parse tree produced by VerilogParser#list_of_block_variable_identifiers.
Exit a parse tree produced by VerilogParser#list_of_block_variable_identifiers.
ctx
the parse tree
abstract def exitList_of_event_identifiers(ctx: List_of_event_identifiersContext): Unit
Exit a parse tree produced by VerilogParser#list_of_event_identifiers.
Exit a parse tree produced by VerilogParser#list_of_event_identifiers.
ctx
the parse tree
abstract def exitList_of_genvar_identifiers(ctx: List_of_genvar_identifiersContext): Unit
Exit a parse tree produced by VerilogParser#list_of_genvar_identifiers.
Exit a parse tree produced by VerilogParser#list_of_genvar_identifiers.
ctx
the parse tree
abstract def exitList_of_net_assignments(ctx: List_of_net_assignmentsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_net_assignments.
Exit a parse tree produced by VerilogParser#list_of_net_assignments.
ctx
the parse tree
abstract def exitList_of_net_decl_assignments(ctx: List_of_net_decl_assignmentsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_net_decl_assignments.
Exit a parse tree produced by VerilogParser#list_of_net_decl_assignments.
ctx
the parse tree
abstract def exitList_of_net_identifiers(ctx: List_of_net_identifiersContext): Unit
Exit a parse tree produced by VerilogParser#list_of_net_identifiers.
Exit a parse tree produced by VerilogParser#list_of_net_identifiers.
ctx
the parse tree
abstract def exitList_of_param_assignments(ctx: List_of_param_assignmentsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_param_assignments.
Exit a parse tree produced by VerilogParser#list_of_param_assignments.
ctx
the parse tree
abstract def exitList_of_parameter_assignments(ctx: List_of_parameter_assignmentsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_parameter_assignments.
Exit a parse tree produced by VerilogParser#list_of_parameter_assignments.
ctx
the parse tree
abstract def exitList_of_path_delay_expressions(ctx: List_of_path_delay_expressionsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_path_delay_expressions.
Exit a parse tree produced by VerilogParser#list_of_path_delay_expressions.
ctx
the parse tree
abstract def exitList_of_path_inputs(ctx: List_of_path_inputsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_path_inputs.
Exit a parse tree produced by VerilogParser#list_of_path_inputs.
ctx
the parse tree
abstract def exitList_of_path_outputs(ctx: List_of_path_outputsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_path_outputs.
Exit a parse tree produced by VerilogParser#list_of_path_outputs.
ctx
the parse tree
abstract def exitList_of_port_connections(ctx: List_of_port_connectionsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_port_connections.
Exit a parse tree produced by VerilogParser#list_of_port_connections.
ctx
the parse tree
abstract def exitList_of_port_declarations(ctx: List_of_port_declarationsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_port_declarations.
Exit a parse tree produced by VerilogParser#list_of_port_declarations.
ctx
the parse tree
abstract def exitList_of_port_identifiers(ctx: List_of_port_identifiersContext): Unit
Exit a parse tree produced by VerilogParser#list_of_port_identifiers.
Exit a parse tree produced by VerilogParser#list_of_port_identifiers.
ctx
the parse tree
abstract def exitList_of_ports(ctx: List_of_portsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_ports.
Exit a parse tree produced by VerilogParser#list_of_ports.
ctx
the parse tree
abstract def exitList_of_real_identifiers(ctx: List_of_real_identifiersContext): Unit
Exit a parse tree produced by VerilogParser#list_of_real_identifiers.
Exit a parse tree produced by VerilogParser#list_of_real_identifiers.
ctx
the parse tree
abstract def exitList_of_specparam_assignments(ctx: List_of_specparam_assignmentsContext): Unit
Exit a parse tree produced by VerilogParser#list_of_specparam_assignments.
Exit a parse tree produced by VerilogParser#list_of_specparam_assignments.
ctx
the parse tree
abstract def exitList_of_variable_identifiers(ctx: List_of_variable_identifiersContext): Unit
Exit a parse tree produced by VerilogParser#list_of_variable_identifiers.
Exit a parse tree produced by VerilogParser#list_of_variable_identifiers.
ctx
the parse tree
abstract def exitList_of_variable_port_identifiers(ctx: List_of_variable_port_identifiersContext): Unit
Exit a parse tree produced by VerilogParser#list_of_variable_port_identifiers.
Exit a parse tree produced by VerilogParser#list_of_variable_port_identifiers.
ctx
the parse tree
abstract def exitLocal_parameter_declaration(ctx: Local_parameter_declarationContext): Unit
Exit a parse tree produced by VerilogParser#local_parameter_declaration.
Exit a parse tree produced by VerilogParser#local_parameter_declaration.
ctx
the parse tree
abstract def exitLoop_statement(ctx: Loop_statementContext): Unit
Exit a parse tree produced by VerilogParser#loop_statement.
Exit a parse tree produced by VerilogParser#loop_statement.
ctx
the parse tree
abstract def exitLsb_constant_expression(ctx: Lsb_constant_expressionContext): Unit
Exit a parse tree produced by VerilogParser#lsb_constant_expression.
Exit a parse tree produced by VerilogParser#lsb_constant_expression.
ctx
the parse tree
abstract def exitMemory_identifier(ctx: Memory_identifierContext): Unit
Exit a parse tree produced by VerilogParser#memory_identifier.
Exit a parse tree produced by VerilogParser#memory_identifier.
ctx
the parse tree
abstract def exitMintypmax_expression(ctx: Mintypmax_expressionContext): Unit
Exit a parse tree produced by VerilogParser#mintypmax_expression.
Exit a parse tree produced by VerilogParser#mintypmax_expression.
ctx
the parse tree
abstract def exitModule_declaration(ctx: Module_declarationContext): Unit
Exit a parse tree produced by VerilogParser#module_declaration.
Exit a parse tree produced by VerilogParser#module_declaration.
ctx
the parse tree
abstract def exitModule_head(ctx: Module_headContext): Unit
Exit a parse tree produced by VerilogParser#module_head.
Exit a parse tree produced by VerilogParser#module_head.
ctx
the parse tree
abstract def exitModule_identifier(ctx: Module_identifierContext): Unit
Exit a parse tree produced by VerilogParser#module_identifier.
Exit a parse tree produced by VerilogParser#module_identifier.
ctx
the parse tree
abstract def exitModule_instance(ctx: Module_instanceContext): Unit
Exit a parse tree produced by VerilogParser#module_instance.
Exit a parse tree produced by VerilogParser#module_instance.
ctx
the parse tree
abstract def exitModule_instance_identifier(ctx: Module_instance_identifierContext): Unit
Exit a parse tree produced by VerilogParser#module_instance_identifier.
Exit a parse tree produced by VerilogParser#module_instance_identifier.
ctx
the parse tree
abstract def exitModule_instantiation(ctx: Module_instantiationContext): Unit
Exit a parse tree produced by VerilogParser#module_instantiation.
Exit a parse tree produced by VerilogParser#module_instantiation.
ctx
the parse tree
abstract def exitModule_item(ctx: Module_itemContext): Unit
Exit a parse tree produced by VerilogParser#module_item.
Exit a parse tree produced by VerilogParser#module_item.
ctx
the parse tree
abstract def exitModule_keyword(ctx: Module_keywordContext): Unit
Exit a parse tree produced by VerilogParser#module_keyword.
Exit a parse tree produced by VerilogParser#module_keyword.
ctx
the parse tree
abstract def exitModule_or_generate_item(ctx: Module_or_generate_itemContext): Unit
Exit a parse tree produced by VerilogParser#module_or_generate_item.
Exit a parse tree produced by VerilogParser#module_or_generate_item.
ctx
the parse tree
abstract def exitModule_or_generate_item_declaration(ctx: Module_or_generate_item_declarationContext): Unit
Exit a parse tree produced by VerilogParser#module_or_generate_item_declaration.
Exit a parse tree produced by VerilogParser#module_or_generate_item_declaration.
ctx
the parse tree
abstract def exitModule_parameter_port_list(ctx: Module_parameter_port_listContext): Unit
Exit a parse tree produced by VerilogParser#module_parameter_port_list.
Exit a parse tree produced by VerilogParser#module_parameter_port_list.
ctx
the parse tree
abstract def exitModule_path_concatenation(ctx: Module_path_concatenationContext): Unit
Exit a parse tree produced by VerilogParser#module_path_concatenation.
Exit a parse tree produced by VerilogParser#module_path_concatenation.
ctx
the parse tree
abstract def exitModule_path_conditional_expression(ctx: Module_path_conditional_expressionContext): Unit
Exit a parse tree produced by VerilogParser#module_path_conditional_expression.
Exit a parse tree produced by VerilogParser#module_path_conditional_expression.
ctx
the parse tree
abstract def exitModule_path_expression(ctx: Module_path_expressionContext): Unit
Exit a parse tree produced by VerilogParser#module_path_expression.
Exit a parse tree produced by VerilogParser#module_path_expression.
ctx
the parse tree
abstract def exitModule_path_mintypmax_expression(ctx: Module_path_mintypmax_expressionContext): Unit
Exit a parse tree produced by VerilogParser#module_path_mintypmax_expression.
Exit a parse tree produced by VerilogParser#module_path_mintypmax_expression.
ctx
the parse tree
abstract def exitModule_path_multiple_concatenation(ctx: Module_path_multiple_concatenationContext): Unit
Exit a parse tree produced by VerilogParser#module_path_multiple_concatenation.
Exit a parse tree produced by VerilogParser#module_path_multiple_concatenation.
ctx
the parse tree
abstract def exitModule_path_primary(ctx: Module_path_primaryContext): Unit
Exit a parse tree produced by VerilogParser#module_path_primary.
Exit a parse tree produced by VerilogParser#module_path_primary.
ctx
the parse tree
abstract def exitMos_switch_instance(ctx: Mos_switch_instanceContext): Unit
Exit a parse tree produced by VerilogParser#mos_switch_instance.
Exit a parse tree produced by VerilogParser#mos_switch_instance.
ctx
the parse tree
abstract def exitMos_switchtype(ctx: Mos_switchtypeContext): Unit
Exit a parse tree produced by VerilogParser#mos_switchtype.
Exit a parse tree produced by VerilogParser#mos_switchtype.
ctx
the parse tree
abstract def exitMsb_constant_expression(ctx: Msb_constant_expressionContext): Unit
Exit a parse tree produced by VerilogParser#msb_constant_expression.
Exit a parse tree produced by VerilogParser#msb_constant_expression.
ctx
the parse tree
abstract def exitMultiple_concatenation(ctx: Multiple_concatenationContext): Unit
Exit a parse tree produced by VerilogParser#multiple_concatenation.
Exit a parse tree produced by VerilogParser#multiple_concatenation.
ctx
the parse tree
abstract def exitN_input_gate_instance(ctx: N_input_gate_instanceContext): Unit
Exit a parse tree produced by VerilogParser#n_input_gate_instance.
Exit a parse tree produced by VerilogParser#n_input_gate_instance.
ctx
the parse tree
abstract def exitN_input_gatetype(ctx: N_input_gatetypeContext): Unit
Exit a parse tree produced by VerilogParser#n_input_gatetype.
Exit a parse tree produced by VerilogParser#n_input_gatetype.
ctx
the parse tree
abstract def exitN_output_gate_instance(ctx: N_output_gate_instanceContext): Unit
Exit a parse tree produced by VerilogParser#n_output_gate_instance.
Exit a parse tree produced by VerilogParser#n_output_gate_instance.
ctx
the parse tree
abstract def exitN_output_gatetype(ctx: N_output_gatetypeContext): Unit
Exit a parse tree produced by VerilogParser#n_output_gatetype.
Exit a parse tree produced by VerilogParser#n_output_gatetype.
ctx
the parse tree
abstract def exitName_of_gate_instance(ctx: Name_of_gate_instanceContext): Unit
Exit a parse tree produced by VerilogParser#name_of_gate_instance.
Exit a parse tree produced by VerilogParser#name_of_gate_instance.
ctx
the parse tree
abstract def exitName_of_instance(ctx: Name_of_instanceContext): Unit
Exit a parse tree produced by VerilogParser#name_of_instance.
Exit a parse tree produced by VerilogParser#name_of_instance.
ctx
the parse tree
abstract def exitNamed_parameter_assignment(ctx: Named_parameter_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#named_parameter_assignment.
Exit a parse tree produced by VerilogParser#named_parameter_assignment.
ctx
the parse tree
abstract def exitNamed_port_connection(ctx: Named_port_connectionContext): Unit
Exit a parse tree produced by VerilogParser#named_port_connection.
Exit a parse tree produced by VerilogParser#named_port_connection.
ctx
the parse tree
abstract def exitNcontrol_terminal(ctx: Ncontrol_terminalContext): Unit
Exit a parse tree produced by VerilogParser#ncontrol_terminal.
Exit a parse tree produced by VerilogParser#ncontrol_terminal.
ctx
the parse tree
abstract def exitNet_assignment(ctx: Net_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#net_assignment.
Exit a parse tree produced by VerilogParser#net_assignment.
ctx
the parse tree
abstract def exitNet_concatenation(ctx: Net_concatenationContext): Unit
Exit a parse tree produced by VerilogParser#net_concatenation.
Exit a parse tree produced by VerilogParser#net_concatenation.
ctx
the parse tree
abstract def exitNet_concatenation_value(ctx: Net_concatenation_valueContext): Unit
Exit a parse tree produced by VerilogParser#net_concatenation_value.
Exit a parse tree produced by VerilogParser#net_concatenation_value.
ctx
the parse tree
abstract def exitNet_decl_assignment(ctx: Net_decl_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#net_decl_assignment.
Exit a parse tree produced by VerilogParser#net_decl_assignment.
ctx
the parse tree
abstract def exitNet_declaration(ctx: Net_declarationContext): Unit
Exit a parse tree produced by VerilogParser#net_declaration.
Exit a parse tree produced by VerilogParser#net_declaration.
ctx
the parse tree
abstract def exitNet_identifier(ctx: Net_identifierContext): Unit
Exit a parse tree produced by VerilogParser#net_identifier.
Exit a parse tree produced by VerilogParser#net_identifier.
ctx
the parse tree
abstract def exitNet_lvalue(ctx: Net_lvalueContext): Unit
Exit a parse tree produced by VerilogParser#net_lvalue.
Exit a parse tree produced by VerilogParser#net_lvalue.
ctx
the parse tree
abstract def exitNet_type(ctx: Net_typeContext): Unit
Exit a parse tree produced by VerilogParser#net_type.
Exit a parse tree produced by VerilogParser#net_type.
ctx
the parse tree
abstract def exitNonblocking_assignment(ctx: Nonblocking_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#nonblocking_assignment.
Exit a parse tree produced by VerilogParser#nonblocking_assignment.
ctx
the parse tree
abstract def exitNotify_reg(ctx: Notify_regContext): Unit
Exit a parse tree produced by VerilogParser#notify_reg.
Exit a parse tree produced by VerilogParser#notify_reg.
ctx
the parse tree
abstract def exitNumber(ctx: NumberContext): Unit
Exit a parse tree produced by VerilogParser#number.
Exit a parse tree produced by VerilogParser#number.
ctx
the parse tree
abstract def exitOrdered_parameter_assignment(ctx: Ordered_parameter_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#ordered_parameter_assignment.
Exit a parse tree produced by VerilogParser#ordered_parameter_assignment.
ctx
the parse tree
abstract def exitOrdered_port_connection(ctx: Ordered_port_connectionContext): Unit
Exit a parse tree produced by VerilogParser#ordered_port_connection.
Exit a parse tree produced by VerilogParser#ordered_port_connection.
ctx
the parse tree
abstract def exitOutput_declaration(ctx: Output_declarationContext): Unit
Exit a parse tree produced by VerilogParser#output_declaration.
Exit a parse tree produced by VerilogParser#output_declaration.
ctx
the parse tree
abstract def exitOutput_identifier(ctx: Output_identifierContext): Unit
Exit a parse tree produced by VerilogParser#output_identifier.
Exit a parse tree produced by VerilogParser#output_identifier.
ctx
the parse tree
abstract def exitOutput_port_identifier(ctx: Output_port_identifierContext): Unit
Exit a parse tree produced by VerilogParser#output_port_identifier.
Exit a parse tree produced by VerilogParser#output_port_identifier.
ctx
the parse tree
abstract def exitOutput_terminal(ctx: Output_terminalContext): Unit
Exit a parse tree produced by VerilogParser#output_terminal.
Exit a parse tree produced by VerilogParser#output_terminal.
ctx
the parse tree
abstract def exitOutput_variable_type(ctx: Output_variable_typeContext): Unit
Exit a parse tree produced by VerilogParser#output_variable_type.
Exit a parse tree produced by VerilogParser#output_variable_type.
ctx
the parse tree
abstract def exitPar_block(ctx: Par_blockContext): Unit
Exit a parse tree produced by VerilogParser#par_block.
Exit a parse tree produced by VerilogParser#par_block.
ctx
the parse tree
abstract def exitParallel_edge_sensitive_path_description(ctx: Parallel_edge_sensitive_path_descriptionContext): Unit
Exit a parse tree produced by VerilogParser#parallel_edge_sensitive_path_description.
Exit a parse tree produced by VerilogParser#parallel_edge_sensitive_path_description.
ctx
the parse tree
abstract def exitParallel_path_description(ctx: Parallel_path_descriptionContext): Unit
Exit a parse tree produced by VerilogParser#parallel_path_description.
Exit a parse tree produced by VerilogParser#parallel_path_description.
ctx
the parse tree
abstract def exitParam_assignment(ctx: Param_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#param_assignment.
Exit a parse tree produced by VerilogParser#param_assignment.
ctx
the parse tree
abstract def exitParameter_declaration(ctx: Parameter_declarationContext): Unit
Exit a parse tree produced by VerilogParser#parameter_declaration.
Exit a parse tree produced by VerilogParser#parameter_declaration.
ctx
the parse tree
abstract def exitParameter_declaration_(ctx: Parameter_declaration_Context): Unit
Exit a parse tree produced by VerilogParser#parameter_declaration_.
Exit a parse tree produced by VerilogParser#parameter_declaration_.
ctx
the parse tree
abstract def exitParameter_identifier(ctx: Parameter_identifierContext): Unit
Exit a parse tree produced by VerilogParser#parameter_identifier.
Exit a parse tree produced by VerilogParser#parameter_identifier.
ctx
the parse tree
abstract def exitParameter_override(ctx: Parameter_overrideContext): Unit
Exit a parse tree produced by VerilogParser#parameter_override.
Exit a parse tree produced by VerilogParser#parameter_override.
ctx
the parse tree
abstract def exitParameter_value_assignment(ctx: Parameter_value_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#parameter_value_assignment.
Exit a parse tree produced by VerilogParser#parameter_value_assignment.
ctx
the parse tree
abstract def exitPass_en_switchtype(ctx: Pass_en_switchtypeContext): Unit
Exit a parse tree produced by VerilogParser#pass_en_switchtype.
Exit a parse tree produced by VerilogParser#pass_en_switchtype.
ctx
the parse tree
abstract def exitPass_enable_switch_instance(ctx: Pass_enable_switch_instanceContext): Unit
Exit a parse tree produced by VerilogParser#pass_enable_switch_instance.
Exit a parse tree produced by VerilogParser#pass_enable_switch_instance.
ctx
the parse tree
abstract def exitPass_switch_instance(ctx: Pass_switch_instanceContext): Unit
Exit a parse tree produced by VerilogParser#pass_switch_instance.
Exit a parse tree produced by VerilogParser#pass_switch_instance.
ctx
the parse tree
abstract def exitPass_switchtype(ctx: Pass_switchtypeContext): Unit
Exit a parse tree produced by VerilogParser#pass_switchtype.
Exit a parse tree produced by VerilogParser#pass_switchtype.
ctx
the parse tree
abstract def exitPath_declaration(ctx: Path_declarationContext): Unit
Exit a parse tree produced by VerilogParser#path_declaration.
Exit a parse tree produced by VerilogParser#path_declaration.
ctx
the parse tree
abstract def exitPath_delay_expression(ctx: Path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#path_delay_expression.
Exit a parse tree produced by VerilogParser#path_delay_expression.
ctx
the parse tree
abstract def exitPath_delay_value(ctx: Path_delay_valueContext): Unit
Exit a parse tree produced by VerilogParser#path_delay_value.
Exit a parse tree produced by VerilogParser#path_delay_value.
ctx
the parse tree
abstract def exitPcontrol_terminal(ctx: Pcontrol_terminalContext): Unit
Exit a parse tree produced by VerilogParser#pcontrol_terminal.
Exit a parse tree produced by VerilogParser#pcontrol_terminal.
ctx
the parse tree
abstract def exitPolarity_operator(ctx: Polarity_operatorContext): Unit
Exit a parse tree produced by VerilogParser#polarity_operator.
Exit a parse tree produced by VerilogParser#polarity_operator.
ctx
the parse tree
abstract def exitPort(ctx: PortContext): Unit
Exit a parse tree produced by VerilogParser#port.
Exit a parse tree produced by VerilogParser#port.
ctx
the parse tree
abstract def exitPort_declaration(ctx: Port_declarationContext): Unit
Exit a parse tree produced by VerilogParser#port_declaration.
Exit a parse tree produced by VerilogParser#port_declaration.
ctx
the parse tree
abstract def exitPort_expression(ctx: Port_expressionContext): Unit
Exit a parse tree produced by VerilogParser#port_expression.
Exit a parse tree produced by VerilogParser#port_expression.
ctx
the parse tree
abstract def exitPort_identifier(ctx: Port_identifierContext): Unit
Exit a parse tree produced by VerilogParser#port_identifier.
Exit a parse tree produced by VerilogParser#port_identifier.
ctx
the parse tree
abstract def exitPort_reference(ctx: Port_referenceContext): Unit
Exit a parse tree produced by VerilogParser#port_reference.
Exit a parse tree produced by VerilogParser#port_reference.
ctx
the parse tree
abstract def exitPrimary(ctx: PrimaryContext): Unit
Exit a parse tree produced by VerilogParser#primary.
Exit a parse tree produced by VerilogParser#primary.
ctx
the parse tree
abstract def exitProcedural_continuous_assignments(ctx: Procedural_continuous_assignmentsContext): Unit
Exit a parse tree produced by VerilogParser#procedural_continuous_assignments.
Exit a parse tree produced by VerilogParser#procedural_continuous_assignments.
ctx
the parse tree
abstract def exitProcedural_timing_control_statement(ctx: Procedural_timing_control_statementContext): Unit
Exit a parse tree produced by VerilogParser#procedural_timing_control_statement.
Exit a parse tree produced by VerilogParser#procedural_timing_control_statement.
ctx
the parse tree
abstract def exitPull_gate_instance(ctx: Pull_gate_instanceContext): Unit
Exit a parse tree produced by VerilogParser#pull_gate_instance.
Exit a parse tree produced by VerilogParser#pull_gate_instance.
ctx
the parse tree
abstract def exitPulldown_strength(ctx: Pulldown_strengthContext): Unit
Exit a parse tree produced by VerilogParser#pulldown_strength.
Exit a parse tree produced by VerilogParser#pulldown_strength.
ctx
the parse tree
abstract def exitPullup_strength(ctx: Pullup_strengthContext): Unit
Exit a parse tree produced by VerilogParser#pullup_strength.
Exit a parse tree produced by VerilogParser#pullup_strength.
ctx
the parse tree
abstract def exitPulse_control_specparam(ctx: Pulse_control_specparamContext): Unit
Exit a parse tree produced by VerilogParser#pulse_control_specparam.
Exit a parse tree produced by VerilogParser#pulse_control_specparam.
ctx
the parse tree
abstract def exitPulsestyle_declaration(ctx: Pulsestyle_declarationContext): Unit
Exit a parse tree produced by VerilogParser#pulsestyle_declaration.
Exit a parse tree produced by VerilogParser#pulsestyle_declaration.
ctx
the parse tree
abstract def exitRange_(ctx: Range_Context): Unit
Exit a parse tree produced by VerilogParser#range_.
Exit a parse tree produced by VerilogParser#range_.
ctx
the parse tree
abstract def exitRange_expression(ctx: Range_expressionContext): Unit
Exit a parse tree produced by VerilogParser#range_expression.
Exit a parse tree produced by VerilogParser#range_expression.
ctx
the parse tree
abstract def exitRange_or_type(ctx: Range_or_typeContext): Unit
Exit a parse tree produced by VerilogParser#range_or_type.
Exit a parse tree produced by VerilogParser#range_or_type.
ctx
the parse tree
abstract def exitReal_declaration(ctx: Real_declarationContext): Unit
Exit a parse tree produced by VerilogParser#real_declaration.
Exit a parse tree produced by VerilogParser#real_declaration.
ctx
the parse tree
abstract def exitReal_identifier(ctx: Real_identifierContext): Unit
Exit a parse tree produced by VerilogParser#real_identifier.
Exit a parse tree produced by VerilogParser#real_identifier.
ctx
the parse tree
abstract def exitReal_type(ctx: Real_typeContext): Unit
Exit a parse tree produced by VerilogParser#real_type.
Exit a parse tree produced by VerilogParser#real_type.
ctx
the parse tree
abstract def exitRealtime_declaration(ctx: Realtime_declarationContext): Unit
Exit a parse tree produced by VerilogParser#realtime_declaration.
Exit a parse tree produced by VerilogParser#realtime_declaration.
ctx
the parse tree
abstract def exitReg_declaration(ctx: Reg_declarationContext): Unit
Exit a parse tree produced by VerilogParser#reg_declaration.
Exit a parse tree produced by VerilogParser#reg_declaration.
ctx
the parse tree
abstract def exitReject_limit_value(ctx: Reject_limit_valueContext): Unit
Exit a parse tree produced by VerilogParser#reject_limit_value.
Exit a parse tree produced by VerilogParser#reject_limit_value.
ctx
the parse tree
abstract def exitRemain_active_flag(ctx: Remain_active_flagContext): Unit
Exit a parse tree produced by VerilogParser#remain_active_flag.
Exit a parse tree produced by VerilogParser#remain_active_flag.
ctx
the parse tree
abstract def exitSeq_block(ctx: Seq_blockContext): Unit
Exit a parse tree produced by VerilogParser#seq_block.
Exit a parse tree produced by VerilogParser#seq_block.
ctx
the parse tree
abstract def exitShowcancelled_declaration(ctx: Showcancelled_declarationContext): Unit
Exit a parse tree produced by VerilogParser#showcancelled_declaration.
Exit a parse tree produced by VerilogParser#showcancelled_declaration.
ctx
the parse tree
abstract def exitSimple_arrayed_identifier(ctx: Simple_arrayed_identifierContext): Unit
Exit a parse tree produced by VerilogParser#simple_arrayed_identifier.
Exit a parse tree produced by VerilogParser#simple_arrayed_identifier.
ctx
the parse tree
abstract def exitSimple_hierarchical_branch(ctx: Simple_hierarchical_branchContext): Unit
Exit a parse tree produced by VerilogParser#simple_hierarchical_branch.
Exit a parse tree produced by VerilogParser#simple_hierarchical_branch.
ctx
the parse tree
abstract def exitSimple_hierarchical_identifier(ctx: Simple_hierarchical_identifierContext): Unit
Exit a parse tree produced by VerilogParser#simple_hierarchical_identifier.
Exit a parse tree produced by VerilogParser#simple_hierarchical_identifier.
ctx
the parse tree
abstract def exitSimple_path_declaration(ctx: Simple_path_declarationContext): Unit
Exit a parse tree produced by VerilogParser#simple_path_declaration.
Exit a parse tree produced by VerilogParser#simple_path_declaration.
ctx
the parse tree
abstract def exitSource_text(ctx: Source_textContext): Unit
Exit a parse tree produced by VerilogParser#source_text.
Exit a parse tree produced by VerilogParser#source_text.
ctx
the parse tree
abstract def exitSpecify_block(ctx: Specify_blockContext): Unit
Exit a parse tree produced by VerilogParser#specify_block.
Exit a parse tree produced by VerilogParser#specify_block.
ctx
the parse tree
abstract def exitSpecify_input_terminal_descriptor(ctx: Specify_input_terminal_descriptorContext): Unit
Exit a parse tree produced by VerilogParser#specify_input_terminal_descriptor.
Exit a parse tree produced by VerilogParser#specify_input_terminal_descriptor.
ctx
the parse tree
abstract def exitSpecify_item(ctx: Specify_itemContext): Unit
Exit a parse tree produced by VerilogParser#specify_item.
Exit a parse tree produced by VerilogParser#specify_item.
ctx
the parse tree
abstract def exitSpecify_output_terminal_descriptor(ctx: Specify_output_terminal_descriptorContext): Unit
Exit a parse tree produced by VerilogParser#specify_output_terminal_descriptor.
Exit a parse tree produced by VerilogParser#specify_output_terminal_descriptor.
ctx
the parse tree
abstract def exitSpecparam_assignment(ctx: Specparam_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#specparam_assignment.
Exit a parse tree produced by VerilogParser#specparam_assignment.
ctx
the parse tree
abstract def exitSpecparam_declaration(ctx: Specparam_declarationContext): Unit
Exit a parse tree produced by VerilogParser#specparam_declaration.
Exit a parse tree produced by VerilogParser#specparam_declaration.
ctx
the parse tree
abstract def exitSpecparam_identifier(ctx: Specparam_identifierContext): Unit
Exit a parse tree produced by VerilogParser#specparam_identifier.
Exit a parse tree produced by VerilogParser#specparam_identifier.
ctx
the parse tree
abstract def exitStamptime_condition(ctx: Stamptime_conditionContext): Unit
Exit a parse tree produced by VerilogParser#stamptime_condition.
Exit a parse tree produced by VerilogParser#stamptime_condition.
ctx
the parse tree
abstract def exitStart_edge_offset(ctx: Start_edge_offsetContext): Unit
Exit a parse tree produced by VerilogParser#start_edge_offset.
Exit a parse tree produced by VerilogParser#start_edge_offset.
ctx
the parse tree
abstract def exitState_dependent_path_declaration(ctx: State_dependent_path_declarationContext): Unit
Exit a parse tree produced by VerilogParser#state_dependent_path_declaration.
Exit a parse tree produced by VerilogParser#state_dependent_path_declaration.
ctx
the parse tree
abstract def exitStatement(ctx: StatementContext): Unit
Exit a parse tree produced by VerilogParser#statement.
Exit a parse tree produced by VerilogParser#statement.
ctx
the parse tree
abstract def exitStatement_or_null(ctx: Statement_or_nullContext): Unit
Exit a parse tree produced by VerilogParser#statement_or_null.
Exit a parse tree produced by VerilogParser#statement_or_null.
ctx
the parse tree
abstract def exitStrength0(ctx: Strength0Context): Unit
Exit a parse tree produced by VerilogParser#strength0.
Exit a parse tree produced by VerilogParser#strength0.
ctx
the parse tree
abstract def exitStrength1(ctx: Strength1Context): Unit
Exit a parse tree produced by VerilogParser#strength1.
Exit a parse tree produced by VerilogParser#strength1.
ctx
the parse tree
abstract def exitSystem_function_call(ctx: System_function_callContext): Unit
Exit a parse tree produced by VerilogParser#system_function_call.
Exit a parse tree produced by VerilogParser#system_function_call.
ctx
the parse tree
abstract def exitSystem_function_identifier(ctx: System_function_identifierContext): Unit
Exit a parse tree produced by VerilogParser#system_function_identifier.
Exit a parse tree produced by VerilogParser#system_function_identifier.
ctx
the parse tree
abstract def exitSystem_task_enable(ctx: System_task_enableContext): Unit
Exit a parse tree produced by VerilogParser#system_task_enable.
Exit a parse tree produced by VerilogParser#system_task_enable.
ctx
the parse tree
abstract def exitSystem_task_identifier(ctx: System_task_identifierContext): Unit
Exit a parse tree produced by VerilogParser#system_task_identifier.
Exit a parse tree produced by VerilogParser#system_task_identifier.
ctx
the parse tree
abstract def exitT01_path_delay_expression(ctx: T01_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#t01_path_delay_expression.
Exit a parse tree produced by VerilogParser#t01_path_delay_expression.
ctx
the parse tree
abstract def exitT0x_path_delay_expression(ctx: T0x_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#t0x_path_delay_expression.
Exit a parse tree produced by VerilogParser#t0x_path_delay_expression.
ctx
the parse tree
abstract def exitT0z_path_delay_expression(ctx: T0z_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#t0z_path_delay_expression.
Exit a parse tree produced by VerilogParser#t0z_path_delay_expression.
ctx
the parse tree
abstract def exitT10_path_delay_expression(ctx: T10_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#t10_path_delay_expression.
Exit a parse tree produced by VerilogParser#t10_path_delay_expression.
ctx
the parse tree
abstract def exitT1x_path_delay_expression(ctx: T1x_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#t1x_path_delay_expression.
Exit a parse tree produced by VerilogParser#t1x_path_delay_expression.
ctx
the parse tree
abstract def exitT1z_path_delay_expression(ctx: T1z_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#t1z_path_delay_expression.
Exit a parse tree produced by VerilogParser#t1z_path_delay_expression.
ctx
the parse tree
abstract def exitT_path_delay_expression(ctx: T_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#t_path_delay_expression.
Exit a parse tree produced by VerilogParser#t_path_delay_expression.
ctx
the parse tree
abstract def exitTask_declaration(ctx: Task_declarationContext): Unit
Exit a parse tree produced by VerilogParser#task_declaration.
Exit a parse tree produced by VerilogParser#task_declaration.
ctx
the parse tree
abstract def exitTask_enable(ctx: Task_enableContext): Unit
Exit a parse tree produced by VerilogParser#task_enable.
Exit a parse tree produced by VerilogParser#task_enable.
ctx
the parse tree
abstract def exitTask_identifier(ctx: Task_identifierContext): Unit
Exit a parse tree produced by VerilogParser#task_identifier.
Exit a parse tree produced by VerilogParser#task_identifier.
ctx
the parse tree
abstract def exitTask_item_declaration(ctx: Task_item_declarationContext): Unit
Exit a parse tree produced by VerilogParser#task_item_declaration.
Exit a parse tree produced by VerilogParser#task_item_declaration.
ctx
the parse tree
abstract def exitTask_port_item(ctx: Task_port_itemContext): Unit
Exit a parse tree produced by VerilogParser#task_port_item.
Exit a parse tree produced by VerilogParser#task_port_item.
ctx
the parse tree
abstract def exitTask_port_list(ctx: Task_port_listContext): Unit
Exit a parse tree produced by VerilogParser#task_port_list.
Exit a parse tree produced by VerilogParser#task_port_list.
ctx
the parse tree
abstract def exitTask_port_type(ctx: Task_port_typeContext): Unit
Exit a parse tree produced by VerilogParser#task_port_type.
Exit a parse tree produced by VerilogParser#task_port_type.
ctx
the parse tree
abstract def exitTerm(ctx: TermContext): Unit
Exit a parse tree produced by VerilogParser#term.
Exit a parse tree produced by VerilogParser#term.
ctx
the parse tree
abstract def exitTerminal_identifier(ctx: Terminal_identifierContext): Unit
Exit a parse tree produced by VerilogParser#terminal_identifier.
Exit a parse tree produced by VerilogParser#terminal_identifier.
ctx
the parse tree
abstract def exitText_macro_identifier(ctx: Text_macro_identifierContext): Unit
Exit a parse tree produced by VerilogParser#text_macro_identifier.
Exit a parse tree produced by VerilogParser#text_macro_identifier.
ctx
the parse tree
abstract def exitTf_decl_header(ctx: Tf_decl_headerContext): Unit
Exit a parse tree produced by VerilogParser#tf_decl_header.
Exit a parse tree produced by VerilogParser#tf_decl_header.
ctx
the parse tree
abstract def exitTf_declaration(ctx: Tf_declarationContext): Unit
Exit a parse tree produced by VerilogParser#tf_declaration.
Exit a parse tree produced by VerilogParser#tf_declaration.
ctx
the parse tree
abstract def exitTfall_path_delay_expression(ctx: Tfall_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#tfall_path_delay_expression.
Exit a parse tree produced by VerilogParser#tfall_path_delay_expression.
ctx
the parse tree
abstract def exitThreshold(ctx: ThresholdContext): Unit
Exit a parse tree produced by VerilogParser#threshold.
Exit a parse tree produced by VerilogParser#threshold.
ctx
the parse tree
abstract def exitTime_declaration(ctx: Time_declarationContext): Unit
Exit a parse tree produced by VerilogParser#time_declaration.
Exit a parse tree produced by VerilogParser#time_declaration.
ctx
the parse tree
abstract def exitTimescale_directive(ctx: Timescale_directiveContext): Unit
Exit a parse tree produced by VerilogParser#timescale_directive.
Exit a parse tree produced by VerilogParser#timescale_directive.
ctx
the parse tree
abstract def exitTiming_check_limit(ctx: Timing_check_limitContext): Unit
Exit a parse tree produced by VerilogParser#timing_check_limit.
Exit a parse tree produced by VerilogParser#timing_check_limit.
ctx
the parse tree
abstract def exitTopmodule_identifier(ctx: Topmodule_identifierContext): Unit
Exit a parse tree produced by VerilogParser#topmodule_identifier.
Exit a parse tree produced by VerilogParser#topmodule_identifier.
ctx
the parse tree
abstract def exitTrise_path_delay_expression(ctx: Trise_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#trise_path_delay_expression.
Exit a parse tree produced by VerilogParser#trise_path_delay_expression.
ctx
the parse tree
abstract def exitTx0_path_delay_expression(ctx: Tx0_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#tx0_path_delay_expression.
Exit a parse tree produced by VerilogParser#tx0_path_delay_expression.
ctx
the parse tree
abstract def exitTx1_path_delay_expression(ctx: Tx1_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#tx1_path_delay_expression.
Exit a parse tree produced by VerilogParser#tx1_path_delay_expression.
ctx
the parse tree
abstract def exitTxz_path_delay_expression(ctx: Txz_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#txz_path_delay_expression.
Exit a parse tree produced by VerilogParser#txz_path_delay_expression.
ctx
the parse tree
abstract def exitTz0_path_delay_expression(ctx: Tz0_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#tz0_path_delay_expression.
Exit a parse tree produced by VerilogParser#tz0_path_delay_expression.
ctx
the parse tree
abstract def exitTz1_path_delay_expression(ctx: Tz1_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#tz1_path_delay_expression.
Exit a parse tree produced by VerilogParser#tz1_path_delay_expression.
ctx
the parse tree
abstract def exitTz_path_delay_expression(ctx: Tz_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#tz_path_delay_expression.
Exit a parse tree produced by VerilogParser#tz_path_delay_expression.
ctx
the parse tree
abstract def exitTzx_path_delay_expression(ctx: Tzx_path_delay_expressionContext): Unit
Exit a parse tree produced by VerilogParser#tzx_path_delay_expression.
Exit a parse tree produced by VerilogParser#tzx_path_delay_expression.
ctx
the parse tree
abstract def exitUdp_identifier(ctx: Udp_identifierContext): Unit
Exit a parse tree produced by VerilogParser#udp_identifier.
Exit a parse tree produced by VerilogParser#udp_identifier.
ctx
the parse tree
abstract def exitUdp_instance_identifier(ctx: Udp_instance_identifierContext): Unit
Exit a parse tree produced by VerilogParser#udp_instance_identifier.
Exit a parse tree produced by VerilogParser#udp_instance_identifier.
ctx
the parse tree
abstract def exitUnary_module_path_operator(ctx: Unary_module_path_operatorContext): Unit
Exit a parse tree produced by VerilogParser#unary_module_path_operator.
Exit a parse tree produced by VerilogParser#unary_module_path_operator.
ctx
the parse tree
abstract def exitUnary_operator(ctx: Unary_operatorContext): Unit
Exit a parse tree produced by VerilogParser#unary_operator.
Exit a parse tree produced by VerilogParser#unary_operator.
ctx
the parse tree
abstract def exitUndef_directive(ctx: Undef_directiveContext): Unit
Exit a parse tree produced by VerilogParser#undef_directive.
Exit a parse tree produced by VerilogParser#undef_directive.
ctx
the parse tree
abstract def exitUse_clause(ctx: Use_clauseContext): Unit
Exit a parse tree produced by VerilogParser#use_clause.
Exit a parse tree produced by VerilogParser#use_clause.
ctx
the parse tree
abstract def exitUsing_defined_flag(ctx: Using_defined_flagContext): Unit
Exit a parse tree produced by VerilogParser#using_defined_flag.
Exit a parse tree produced by VerilogParser#using_defined_flag.
ctx
the parse tree
abstract def exitVariable_assignment(ctx: Variable_assignmentContext): Unit
Exit a parse tree produced by VerilogParser#variable_assignment.
Exit a parse tree produced by VerilogParser#variable_assignment.
ctx
the parse tree
abstract def exitVariable_concatenation(ctx: Variable_concatenationContext): Unit
Exit a parse tree produced by VerilogParser#variable_concatenation.
Exit a parse tree produced by VerilogParser#variable_concatenation.
ctx
the parse tree
abstract def exitVariable_concatenation_value(ctx: Variable_concatenation_valueContext): Unit
Exit a parse tree produced by VerilogParser#variable_concatenation_value.
Exit a parse tree produced by VerilogParser#variable_concatenation_value.
ctx
the parse tree
abstract def exitVariable_identifier(ctx: Variable_identifierContext): Unit
Exit a parse tree produced by VerilogParser#variable_identifier.
Exit a parse tree produced by VerilogParser#variable_identifier.
ctx
the parse tree
abstract def exitVariable_lvalue(ctx: Variable_lvalueContext): Unit
Exit a parse tree produced by VerilogParser#variable_lvalue.
Exit a parse tree produced by VerilogParser#variable_lvalue.
ctx
the parse tree
abstract def exitVariable_type(ctx: Variable_typeContext): Unit
Exit a parse tree produced by VerilogParser#variable_type.
Exit a parse tree produced by VerilogParser#variable_type.
ctx
the parse tree
abstract def exitWait_statement(ctx: Wait_statementContext): Unit
Exit a parse tree produced by VerilogParser#wait_statement.
Exit a parse tree produced by VerilogParser#wait_statement.
ctx
the parse tree
abstract def exitWidth_constant_expression(ctx: Width_constant_expressionContext): Unit
Exit a parse tree produced by VerilogParser#width_constant_expression.
Exit a parse tree produced by VerilogParser#width_constant_expression.
ctx
the parse tree
abstract def visitErrorNode(arg0: ErrorNode): Unit
Definition Classes
ParseTreeListener
abstract def visitTerminal(arg0: TerminalNode): Unit
Definition Classes
ParseTreeListener

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def finalize(): Unit
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Deprecated
(Since version 9)

Packages

VerilogParserListener

trait VerilogParserListener extends ParseTreeListener

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VerilogParserListener

trait VerilogParserListener extends ParseTreeListener

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VerilogParserListener